This is designed to be a quick overview of the most common 82574 software questions we get. This is not designed to replace a reading of the datasheet and spec update. In fact, the datasheet and spec update are required reading and if they conflict, the datasheet and spec update are right and this page is wrong. If you like this type of FAQ, leave us a comment and maybe we will do more of them. Also, we may not update this page in the future so I can’t say this enough; check the datasheet and spec update!
Q: Can the 82574 support IEEE1588?
A: It is available over the PCIe* bus but the support in the software is limited. Ask your O/S vendor what they can support.
Q: How can a customer hot-plug an 82574 into a docking station?
A: Have them read the hot plug section of the PCIe spec. They will have to implement hot-plug events through the PCI Express bridge device which includes a bunch of FGA code and/or PCIe bridge configuration.
Q: How can I disable ASPM?
A: Disable ASPM on the 82574 side by clearing bits 1:0 in config space offset 0xf0. To enable ASPM these bits need to be set to 0x3. This can also be accomplished through the EEUpdate menu.
Q: Does 82574 or Intel(R) Gigabit CT Desktop Adapter support teaming?
A: 82574 can initiate a team as a LOM and when on an Intel(R) Gigabit CT Desktop Adapter.
Either one can be a team member also.
Q: Does Intel(R) Gigabit CT Desktop Adapter belong to the Server or Desktop NIC Card category?
A: Interesting question! If you look at the Branding String – it is a Desktop Card – however, everything else follows server card rules such as – it will initiate teaming.
Q: When forcing speed to 1GbE in software using CTRL.FRCSPD and setting the PHY to the same speed as required, what happens when it is set up for WOL, the part goes from D0 to D3 state and the PHY speed setting changes to 10Mbs while the MAC retains its 1GbE setting?
A: Our devices do not connect at 1Gbps in lower power states, so the link will be disconnected in Sx states even when WOL is enabled if the link speed is forced to 1Gbe only.
Q: I’m using the 82574 to output system status through the LED pins using SW registers. There is a delay between writing to the register and the LED changing (2-300 µs when cable is unplugged and 3-400µs when cable is plugged in). I want to make the delay as small as possible.
A: The part was not designed or marketed for this type of functionality. The HW blink mechanism causes the delay to ensure that ON pulses are visible to the human eye for the LED pins. This delay can be reduced by setting the BLINK_MODE bit to 1, but it cannot be eliminated. When there is no link, the internal clock runs 5x slower, so the turn-off time becomes correspondingly longer. (See Note 3 at the end of the LEDCTL section in the datasheet.)
The following table shows the ON time for different modes.
BLINK_MODE = 0 (200 ms)
BLINK_MODE = 1 (83 ms)
0-34 + n*201 ms
0-14 + n*83 ms
0-168 + n*1007 ms
0-70 + n*415 ms
Option A: Increase the SW blink time from 500 ms to 1000 ms. Then the turn-off delay will be less than 180 ms even when the link is down, and the duty cycle will look much better.
Option B: Set BLINK_MODE to 1 (for all 3 LEDS - this will also increase the blink rate for LED2). Change the SW blink time to something like 400 ms or 820 ms, with a resulting turn-off delay of less than 100 ms.
Q: What IEEE Test Modes are offered for 82574? How can I perform those tests? What about Jitter Tests?
A: We have a tool called LANConf that is available under CNDA to help speed that along. Ask your Intel representative to help get you a copy.
If you don’t have it, here’s exactly what we do in the code
- Write 0x140 to register 0
- Read register 0
- NAND with 0x1000
- Write value to register 0
- Read register 9
- NAND with 0xFF00 to turn off all test modes(set bits 8-15 off)
- Write register 9 with value
- Delay 1 second
- Read register 9
- If TM1
o OR read value with 3B00
- If TM2
o OR read value with 5B00
- If TM3
o OR read value with 7B00
- If TM4
o OR read value with 9B00
- Write register 9 with value.
For gigabit, none of our Gigabit controllers should ever change; they are always on Register 9 bits 15:13. This is specified by the IEEE spec (802.3ab).
To do 100Mb it varies:
100Mb test modes for 82574 are specified on register 0x1A in bits 3:2. In order to do this you need
1) Write 0x2000 to Register 0 to force 100Mb mode <Result: Scrambled idle 100Mb communication on MDI>
2) Write desired 100MB test mode value to Register 0 <0x0040 by default, 0x0048 for 112ns, and 0x004C for 16ns pulses>
112ns Pulse – Turn on bit 3, turn bit 2 off
16ns pulse – Turn on bit 3, turn on bit 2.
Outputting 10MB is not possible through test modes. In order to output 10MB signals for IEEE testing for 82574 you need to send certain sized packets with specific data inside.
Q: Is there a way to check if the 82574 has reported bad TLP or DLLP without using an analyzer?
A: Yes. Check the Correctable Error Status register, 0x110 in the PCIe config space. See bit definitions in the datasheet (Note that the 0x10 listed in the datasheet is an offset from the PCIe Extended Configuration Space that starts at 0x100), You can view this by looking at the PCIe Raw display using your favorite PCI config space tool.