At Intel we have some rather elaborate IEEE test automation capabilities. Every NIC (network interface card) manufactured by Intel and every LOM (LAN on motherboard) is tested against the IEEE spec for conformance multiple times through our development cycle. In addition to testing our own products we can test customer designs that are using Intel PHYs.
Over the years we have developed a client/server automation software package called “Network Product Platform Validation” or NPPV for short. This software works with a suite of different types of test instruments. We use custom designed test boards with relays on them to set up the different loads and instrumentation required for all of the different IEEE tests. These boards have integrated 100 ohm test loads for all four pairs, 50 – 100 ohm balun test fixtures, differential breakout fixtures, common-mode output voltage test fixture, and an alien crosstalk test fixture. Below is a picture of the transmit (or TX) board used to run the IEEE transmit testing.
We also use a receive (or RX) board that is connected to cables that can test against different lengths for the IEEE Bit Error Rate (BER) tests for 10Mb/100Mb/1000Mb as well as testing Alien Crosstalk and Common-Mode Noise Rejection. To generate the traffic for the BER tests we usually use an Intel® 82540 NIC, which is one of the cleanest client network cards designed in the past to provide the highest quality input signal for the test. Below is a picture of what our BER setup looks like. Each connector has a different length cable connection and those can be concatenated to create the different lengths in our BER testing. The automation software controls the switches on the board to make the different lengths.
Before any of these boards are used they go through a rigorous characterization to ensure that each onboard fixture and BER cable length is consistent with our other boards and that they match the test results from using a manual test fixture.
Besides these custom boards, our test stations use a variety of digitizing scopes capable of up to 8 GHz bandwidth, network analyzers, high-bandwidth differential probes with capacitance less than 1 pF greater than 1 GHz bandwidth, a waveform generator, and a function generator. A switch system is used to control the relays on the test boards to set up each test. We also have a VNA calibration load fixture that is used to calibrate the network analyzer before any return loss testing. This is done before every return loss test is done because air temperature and humidity changes can affect the results.
The automation software is impressive as well. It is capable of resetting and configuring each instrument before the tests are run. Once a test is started it will look through each 10Mbit, 100Mbit, and Gigabit test collecting and storing data on our secure server. The automation software can intelligently go through each test tuning the trigger levels and other aspects of the scopes. For example, as the common mode output voltage test for gigabit is running (18.104.22.168) it will physically change switches on our custom test board to route the output of Pair A through the common mode output voltage fixture. It then will set the scope to the correct horizontal/vertical scale, vertical range, trigger type, trigger level, and trigger mode. It will first step the cursor in the positive direction just until the trigger is lost and then toggle the trigger back and forth finding the ideal point just before it can’t trigger anymore. At that point the display persistence is changed, the common mode noise is sampled and the graph is generated. We change the colors to make it look nice and pretty for the customer. J This is repeated for the negative triggering and for pairs B through D. In addition to our “pretty” graphs we put the noise level for positive and negative in a table so the values can be easily viewed. Below is a snapshot from our final report showing the results of the 22.214.171.124 Common Mode output voltage test on an Intel Customer Reference Board. In this particular example our PHY passed with lots of margin which goes to show it is a quality PHY, with a good design following our layout requirements, and using good quality magnetics.
Once all of the tests are run, including the Bit Error Rate, the software can build a fairly comprehensive excel spreadsheet (see example above) that has all of the data captured for 10Mbit, 100Mbit, and Gigabit. This is our final report that we can give to customers for analysis. This format makes it very easy to identify problems and see the results. It is also easy to compare the results from different designs between different fab revisions to see how IEEE is affected. Over the years at Intel we have built up a lot of knowledge on a wide variety of design decisions and how they impact IEEE. This knowledge continues to evolve in our design guides and schematic/layout checklists that we provide to board design engineers to enable them to do better LAN design from the beginning.
Our test stations are fairly complex but they save a lot of time over manual testing and allow us to run thousands of different designs and board revisions through IEEE testing. We have this capability to test in several geographies. The majority of customer testing for ODMs (Original Design Manufacturers) is done in Taiwan, where many of them are located, for onsite support. Because a lot of the design and architectural work for Intel is done in Israel, the initial IEEE testing and tuning of the LAN PHY’s is done there. Israel might test a customer platform if it requires some kind of specialized NVM tuning to pass a particular test, but generally that is rare because most IEEE failures can be fixed by focusing on the analog front end with better board designs or better magnetics. Oregon, in the United States, has the most IEEE test stations and is where the automation software was developed. A lot of NICs and customer platforms go through these stations. The Oregon lab will soon be upgraded with new scopes that have the bandwidth to handle future 10 Gigabit testing. This testing is being developed in Oregon and will eventually roll out to each worldwide lab.
If you have a board design with an Intel PHY for which you would like to see IEEE conformance results, contact your local Intel FAE to find out how you can get connected.