ECC has many real "definitions" - error correcting circuits, error correcting code, or error correction code - but they all do the same thing.  It helps keep data intact within the chip memory.   ECC uses a special algorithm to encode information in a block of bits that contains sufficient detail to permit the recovery of a single bit error in the safeguarded data.  This protocol will not only detect single bit errors, but will transparently correct them on the fly.   Double errors will be flagged as an error and the device will try to get software’s attention about it.  Related to ECC is parity.  Parity will keep track of the quantity of bits in total and track them as either even or odd.  Should this parity change while it is in the chip memory, it will be flagged as an error.  Since you can’t tell which bit went rogue, this is a poor man's protection. Also, if more than 1 bit changes, parity check can miss it.

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Product

Packet Buffer

(In band Traffic)

Managability

(out of band traffic)

Datasheet Info

X540

ECC

ECC

7.14.1

82599

ECC

ECC

7.14.1

82598

ECC

ECC

Look for DHER/PBUR

I350

ECC

ECC

7.6

82580

ECC

ECC

7.23

82575 and 82576

ECC

ECC

7.6

82571

ECC

Parity

13.7

82573 /  82574 / 82583

None

None

n/a

82546

None

None

n/a


Both ECC and parity have a basic limitation in that if the error is large enough, it will look okay.  ECC is far more resistant to this.  We try to make sure bad things don't happen to your data, but it still might happen.  And while it will try to tell you when it does go bad, sometimes it still won't notice.  That's why our lawyers care about articles like this.  Multiple bit errors are very rare and probably will cause other problems to the machine.  Data integrity isn't made with a single point safety net.  If you want to guarantee your data, use a multiple layered approach since it’s unlikely that all of them will fail.