One of the key features that contribute to the dramatic performance of Intel’s Ethernet switch architecture is its output-queued shared memory technology. For many years now, academia has extolled the virtues of an output-queued architecture for high-performance switch chip designs. But it has been difficult for any company in the industry to achieve output queuing due to the high memory bandwidth required between the switch inputs and outputs.


Because of this, most vendors implement a combined input-output queued (CIOQ) architecture, which needs less core memory bandwidth, but requires extra features to avoid blocking.  For example, one way to minimize blocking is to provide virtual output queues at each ingress port, but for an N-port switch, this means N*N input queues and associated schedulers, which adds significant complexity.


With Intel® Ethernet switch silicon, the single shared memory array is implemented alongside our crossbar switching technology to provide the capability to support a fully non-blocking output queued, shared memory architecture with extremely low cut-through latency.  It also provides superior multicast bandwidth and jitter for applications such as video distribution. We feel that Intel has the only technology that can provide one of the highest bandwidth Ethernet switch chips in the industry while maintaining less than 400nS cut-through latency.