Routing Differential LAN traces
I work with a TME in LAD who is tasked with reviewing design from our customers. Most times they follow the guidance we give them in our datasheets and reference designs, completing the schematic with little or no customization. Where he does most of my work is in the layout reviews, where the schematics is "put to fab" and traces and components are put in physical locations on a PCB layout. As many companies have shrunk in size and have chosen to outsource engineering resources around board layout, many companies outsource this function. The DE at the company is responsible for finalizing the schematics and passing them on to a 3rd party that interprets the schematics and the guidelines that have been given for the design, typically a physical definition of what he board is supposed to look like. Is it a typical ATX motherboard? Is it an ATCA Mezz card? Or something completely custom to meet a very specific need? The layout person will be the Dr Jekyll/Hyde and bring the Franken-schematic to life!
In the hundreds of reviews that he does for our customers, he tries to find things in their designs that will help them save time and money. They will save time by having him look at the design to make sure that routes are optimal and are per our recommendations in our layout checklists. They will save money because the RED flags that he will catch and fix for them will save them a board spin, which translates into time and money: all things customers like to have. The biggest problem that he sees is when 3rd parties do layouts for my customer is that they use the big fat AUTO-ROUTE button (similar to red EASY button used in commercials from the office supply store, where hitting this red button, makes it EASY for customer to buy stuff). This AUTO-ROUTE button does most of the work for the layout person, if he has defined all he interfaces and pins on the chip accurately. What he means is if they have done a good job of defining the type of I/O that is used on every pin on the chip... Is a pin a digital I/O? Is it open drain? Is it SERDES? Is it providing power? Each of these types of signals has to be cared for differently when you actually "put metal" between the pins of the chips. As he will often say to colleagues as they are doing a first layout review is "the schematic will lie to you".
When first opening a board file, immediately look at how the MDI differential pair are routed. These are found on all of our 10/100 and gigabit silicon and are used to connect the PHY to the magnetics or transformer on the board. These are often time the ONLY analog signaling on the ENTIRE board. Typically they are only designed to drive minimal distances across the board to the XFMR and since they are a pair of complementary signals, they need to be routed symmetrically so that any board parasitics will affect both signals, not just one... Actually, you want to avoid all adverse affects of board parasitics like vias, broadside coupling, etc..
This pair of differential signals (2 with 10/100 and 4 with gigabit) needs to routed with care. Best Rule of Thumb items are:
1.) Route symmetrically as best as you can
2.) Avoid using vias for routing these traces: route a pair on the same board layer
3.) Follow inter-pair (greater than 5x the height of the board dielectric) and intra-pair (<10mil) distance guidance as given in the layout checklist
4.) For gigabit designs, to achieve #3 easily, route two pairs on one layer and the remaining two pairs on another layer
5.) Route on layers that are isolated to good grounds: don't route on layer that is next to another signal layer <- avoids broadband coupling
6.) Differential pairs need to be length matched to within 50 mils... They don't need to be exactly the same length
7.) Target 100 ohm differential impedance
Following these simple layout rules and you will save time and money...
Good definition of Differential signaling : http://en.wikipedia.org/wiki/Differential_signaling
Dr Howard Johnson has a fantastic book "High Speed Digital Design" that can be summed up in a few words - "Model Everything".