• Default memory consistency model of SCC

    Hi, I have got some questions: (i am not using RCCE)   I am using uncached memory (/dev/rckncm) and I have L2 cache disabled (using SCCGui), in this case what will be the memory consistency model on SCC?  ...
    Nil
    created by Nil
  • Relation between CPU freq and Memory freq

    Hi once again,   I have studied about power policy on SCC. But in several paper(especially on DVFS-related paper), they mentioned that, when the CPU frequency set to decrease, it will be the same as Memory(decr...
    chan seok kang
    last modified by chan seok kang
  • How does sccLinux knows which frequency it is running?

    After changing frequency (i am using Fdiv from rcce to do that)  i checked GCBCFG register (using sccGui) and i can see that frequency word has changed. but then i looked at /proc/cpuinfo (by logging into core) a...
    Nil
    created by Nil
  • How to check data in shared memory.

    Hi I`m new to develop linux device driver in SCC. I just wonder how to check the data in shared memory. As you can see that, LUT points the physical Address of Shared MCH0 ~ MCH3. and there are reserved space in the...
    chan seok kang
    created by chan seok kang
  • Question when creating shared memory on SCC by means of LUT remapping.

    I am trying to configure some shared memory on SCC by LUT mapping. I am not using RCCE. Let’s assume i am using core 0, 1, 2, and 3 (only these cores are booted with Linux) . Now I write LUT entries 0x29 (41) to...
    Nil
    created by Nil
  • Changing voltage directly on SCC does not work as expected

    Hi,   I am trying to change voltage directly on SCC by means of writing to RPC using  setvolt application from https://communities.intel.com/thread/26799. The problem is that when i set voltage for example ...
    Nil
    created by Nil
  • Strange, but regular, long-term power fluctuations on SCC

    Hi everyone, it has been a while,   We have recently been working on gathering power measurements from the SCC. As everyone else who has worked on power measurements on the SCC knows; the resolution of the ADC o...
    mwvantol
    last modified by mwvantol
  • MARC Lab Data Center connectivity down

    Currently the MARC lab is not accessible.  We are working with the ISP to resolve this connectivity issue.  We will post a reply when the connectivity issue is resolved.
    mwaughex
    last modified by mwaughex
  • No access

    can't http://marcbug.scc-dc.com/bugzilla3/  or the data center, anyone else experiencing issues with access to the data center hosted MCPCs??
    Ivan Walulya
    created by Ivan Walulya
  • Weird phenomenon about power of SCC chip: more cores booted, less power comsumption

    Hi All,   When using Barrelfish installed on SCC, I found a weird phenomenon that, the more number of cores which I boot Barrelfish on, the less power (exactly the current, the voltage do not change) whole chip&...
    dagger
    last modified by dagger
  • SCC as a shared memory system

    Hi,   is it possible to configure SCC in such a way that it behaves as it was shared memory system (linux running on cores). i.e creating some structure on core 0 and pass pointer to core 1  where core 1 ca...
    Nil
    last modified by Nil
  • Problem in using TSR to implement lock

    Hi,   I am experiencing some problem in using TSR to implement a lock.   I have written a test case where I access TSR for "core 0" (from core 0). At beginning I set TSR to “1” so that next rea...
    Nil
    last modified by Nil
  • Can't get core dumps from programs crashed

    Cross post for Nil. ##http://marcbug.scc-dc.com/bugzilla3/show_bug.cgi?id=512   I'm trying to track what cause a segmentation fault in my SCC program. Since I don't have gdb installed in the cores, I try to ma...
    mwaughex
    last modified by mwaughex
  • Memory consistency issue using RCCE

    Posting this to main forum, incase missed in sub-community.   http://communities.intel.com/message/182388
    mwaughex
    created by mwaughex
  • RCCE bug: Bug in implementation of RCCE_reduce

    I recently found a bug in the implementation of RCCE_reduce. The function runs correctly with the assumption that the root node performing the computation does not require input buffer after calling the function. Th...
    mwaughex
    created by mwaughex
  • Using RCCE alongwith RCKMPI

    Hi all,   I want to use RCCE power function in an MPI application but I am not sure whether this is possible using RCKMPI. I wanted to know if there is any way I can use RCCE power functions like RCCE_iset_power...
    nitesh
    last modified by nitesh
  • DDR3 power in the result of "sccBmc -c stutas"

    Hi all, As you know, there is a "1V5" item in the result of "sccBmc -c stutas". Does this mean the voltage and the current of the main memory?   I found in the experiments, when the cores are accessing MPB, ...
    dagger
    created by dagger
  • Write Combine Buffer status

    Hi,   Is there a way to know the write combine buffer when is full or flushing? Or, does hardware support register to know status of WCB?   Thanks in Advance
    Hayder
    created by Hayder
  • MPB reading gives incorrect result

    Hi,   I have some questions regarding MPB behaviour. In my test program I have allocated MPB memory using MPBalloc from config.c/h (provided with AccessFPGA program). Then I create local buffer to hold data and...
    Nil
    last modified by Nil
  • Baremetal applications - separate tasks for cores

    Hi,   I was experimenting with the Baremichael baremetal framework. Typical applications has the format..   if (get_my_coreid() == 0){   ..... } else if(get_my_coreid() == 1){ ..... }   I ...
    Isuru Nawinne
    last modified by Isuru Nawinne