Hi db4, Thanks for your question. I found the information you are looking for here in the Intel® Xeon® Processor 5500 Series, Datasheet Volume 1.

Now, I'm sure you don't want to really read the whole thing, so to make it easier to answer this specific question, here is the section that may interest you.

2.3 Mixing Processors

Intel supports dual processor (DP) configurations consisting of processors:

1. from the same power optimization segment

2. that support the same maximum Intel QuickPath Interconnect and DDR3 memory

speeds

3. that share symmetry across physical packages with respect to the number of

logical processor per package, number of cores per package, number of Intel

QuickPath interfaces, and cache topology

4. that have identical Extended Family, Extended Model, Processor Type, Family Code

and Model Number as indicated by the function 1 of the CPUID instruction

Note: Processors must operate with the same Intel QuickPath Interconnect, DDR3 memory,

and core frequency.

While Intel does nothing to prevent processors from operating together, some

combinations may not be supported due to limited validation, which may result in

uncharacterized errata. Coupling this fact with the large number of Intel Xeon

Processor 5500 series attributes, the following population rules and stepping matrix

have been developed to clearly define supported configurations.

1. Processors must be of the same power-optimization segment. This insures

processors include the same maximum Intel QuickPath interconnect and DDR3

operating speeds and cache sizes.

2. Processors must operate at the same core frequency. Note, processors within the

same power-optimization segment supporting different maximum core frequencies

(e.g. a 2.93 GHz / 95 W and 2.66 GHz / 95 W) can be operated within a system.

However, both must operate at the highest frequency rating commonly supported.

Mixing components operating at different internal clock frequencies is not

supported and will not be validated by Intel.

3. Processors must share symmetry across physical packages with respect to the

number of logical processors per package, number of cores per package (but not

necessarily the same subset of cores within the packages), number of Intel

QuickPath interfaces, and cache topology.

4. Mixing dissimilar steppings is only supported with processors that have identical

Extended Family, Extended Model, Processor Type, Family Code and Model Number

as indicated by the function 1 of the CPUID instruction. Mixing processors of

different steppings but the same model (as per CPUID instruction) is supported.

Details regarding the CPUID instruction are provided in the AP-485,

Intel® Processor Identification and the CPUID Instruction application note and the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.

5. After AND’ing the feature flag and extended feature flags from the installed

processors, any processor whose set of feature flags exactly matches the AND’ed

feature flags can be selected by the BIOS as the BSP. If no processor exactly

matches the AND’ed feature flag values, then the processor with the numerically

lower CPUID should be selected as the BSP.

6. Intel requires that the proper microcode update be loaded on each processor

operating within the system. Any processor that does not have the proper

microcode update loaded is considered by Intel to be operating out of specification.

7. Customers are fully responsible for the validation of their system configuration.

Let us know if this answers your question.