I have a few questions about the on-chip network of Intel SCC. Please help me understand how hops are counted on the on-chip network. Thanks in advance!
As far as I understand the links between the routers are unidirectional so that brings up the questions: Do the right-most routers wrap-around and directly connect to the left-most routers (i.e., 1 hop away)? Similarly, are the bottom-most routers 1-hop away from the top-most routers?
On a related note, Is access to the closest memory channel also limited by the unidirectionality of the network? So the number of hops to reach the closest memory channel will increase with the number of hops.
Is it possible to reprogram the routers to implement a new routing algorithm or the route between any pair of tiles is fixed?
1. They are bidirectional. Routing is deterministic, XY to be more precise. This means that, on the path from the source to the destination tile, you first completely traverse the x axis, and then the y axis. As a consequence, when a packet travels from core A to core B, it traverses a different set of routers than when it travels from B to A (unless A and B are in the same row or column).
2. You just go to the closest memory controler to your tile.
3. No, the routes are fixed as described under 1).
If you could provide one more clarification that would be great.
The connectivity of the routers at the edges of the mesh is not clear to me yet. If you consider routers 1,2,3,4,5,6 in that order from left to right, are router #1 and router #6 one hop away? I mean do they wrap-around? Similarly I've question about the routers at the edges of all the columns.
I suspect that the answer to that is a No looking at the pictures of the Intel SCC mesh topology. However, the description of the wrapped wavefront arbiter confused me a bit.