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Hi, Is there a way to know the write combine buffer when is full or flushing? Or, does hardware support register to know status of WCB? Thanks in Advance Write Combine Buffer statusBack Hi, Is their a way to get a block of memory (MPB) marked as non cacheable? Thanks in Advance Regards Hayder A non-cacheable block of memoryBack Hi All, We want to buy new MCPC hardware. Did anyone test alternate hardware because the Intel DX58SO and HP Proliant ML110 G6 are discontinued? Thanks in Advance. Hayder Back Hello everyone, I would like to using POP-SHM as a stand-alone library. So, How do I enable pop-shm buffer in SCC-linux (sccKit 1.4.2)? Thanks Hayder Hi, This is new document that is available in Internet: A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. Regards Hayder Hello to everyone, I have some confusion when I use RCCE_comm_split routine. Can anyone to explain me the features and how to using this function? What is happening when make Multiple calls to RCCE_comm_split?... Create a new communicatorBack Hi for all, Actually, I have confused in this code. char buf; for (n=0; n<=1000; n+=100) RCCE_recv(&c, n, 0);  ... Hello, I am new in the SCC, and I have questions about communication between the cores. 1. Can a core execute more than one send and receive operations (message) simultaneously? 2. Can a core identify the signal from ...