I finally finshed the content for the talk that I am scheduled to deliver next week at IDF on Sept 22 (TCIS001 10:15 am – Room 2004).  The content covers examples of optimizing for multi-core using our software tools to accelerate performance,  and more importantly the seamless use of the same software base with minimal or no changes in next-generation architectures (what we call scaling performance forward). Personally, I am excited about the potential of multi-core optimizations with today’s architectures. When I was a graduate student in parallel computing from 1988-1994, it was extremely difficult to take any algorithm and map it to the parallel architectures since most of the algorithms were not very efficient once you took the communication delay’s into account.  The key is to get total delivered performance at an application level, not at the kernel level. However, given the architectures of today which are better balanced, and the availability of multi-core, the memory bandwidth, software tools that work, and the faster interconnects, the number of algorithms that can be parallelized and that actually benefit with accelerated performance (Delivered total application time)  is huge, pretty much every industry vertical is taking advantage of multi-core architectures, software tools, and clusters.

John Gustafson, from our Intel Labs, an industry HPC veteran, is my co-author, and I am thrilled to have him speak about Balanced Computing. Wes Shimanek, a colleague of mine at Intel introduced me to John and after listening to his explanation of balanced computing, and his views on what works and what doesn’t, we immediately  knew that John’s expertise will be greatly valued by the IDF audience, and invited John to be part of the talk. John graciously accepted to participate, and I hope that folks interested in computing architectures, especially in the HPC world will make the time to come listen to John’s talk.

I will also be giving you a high level view on the challenges that drive our products and briefly introduce you to the various aspects of our strategy. I will be followed by 3 more talks that will cover the key aspects of what we do at Intel in HPC, Software Tools for Scaling Application Performance Forward (TCIS002), Delivering more to HPC than just Performance (TCIS003), and Intel® Cluster Ready (TCIS009).

I am looking forward to IDF next week. See you all at the developer forum

Nash Palaniswamy (Intel)

Today Intel provided a server product update for the upcoming Nehalem-EX processor and the expandable platforms based on it.  Here’s a recap of some of the interesting messages communicated to the press:

• Nehalem Architecture and Quick Path Architecture are coming to the EX (MP) segment, 4 Socket Servers and above. 
• EX Servers are ideal for server consolidation / virtualized applications, data demanding enterprise applications and technical computing environments.  Both Itanium and Xeon processors based systems represent an attractive alternative to more expensive, proprietary RISC-processor based systems.
• EX Servers are designed for the high-end.  They offer more capabilities (i.e. memory, RAS, cores/threads, sockets) than 2 Socket Servers that IT managers require for business drivers such as large scale server consolidation, high data demands, virtualization, and scalability.
• Up to eight cores / 16 threads and a whopping 24MB of cache.
• Up to 9x the memory bandwidth vs. today’s 4-Socket Xeon 7400.  The performance will be dramatic – the highest-ever jump from a previous generation processor. 
• 2x the memory capacity with up to 16 memory slots per socket (that’s 64 DIMMs on a 4 Socket Server), and four high-bandwidth QuickPath Interconnect links.
• New levels of scalability: from large memory 2 socket systems through 8 socket systems, and even more with OEM node controllers.  Matter of fact, there are over 15 8-Socket+ designs from 8 OEMs currently. 
• IBM showed their 8S Nehalem-EX server design running 128 threads (8 Sockets x 8 cores x 2 threads due to Hyper Threading)…an industry first. 
• New RAS features traditionally found on Itanium, such as Machine Check Architecture (MCA) Recovery which detects CPU, memory, and I/O errors, works with the OS to correct, and helps recover from otherwise fatal system errors. 
• Nehalem-EX is scheduled for production in the second half of 2009, with OEM systems in early 2010.

Stay tuned over the next few days – we’ll post a video from the event.  Also look for some informative blogs over the next 1-2 weeks that will offer more of an in depth view of Nehalem-EX’s 4 Socket capabilities, performance, scalability, RAS, and Virtualization.