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I finally finshed the content for the talk that I am scheduled to deliver next week at IDF on Sept 22 (TCIS001 10:15 am – Room 2004).  The content covers examples of optimizing for multi-core using our software tools to accelerate performance,  and more importantly the seamless use of the same software base with minimal or no changes in next-generation architectures (what we call scaling performance forward). Personally, I am excited about the potential of multi-core optimizations with today’s architectures. When I was a graduate student in parallel computing from 1988-1994, it was extremely difficult to take any algorithm and map it to the parallel architectures since most of the algorithms were not very efficient once you took the communication delay’s into account.  The key is to get total delivered performance at an application level, not at the kernel level. However, given the architectures of today which are better balanced, and the availability of multi-core, the memory bandwidth, software tools that work, and the faster interconnects, the number of algorithms that can be parallelized and that actually benefit with accelerated performance (Delivered total application time)  is huge, pretty much every industry vertical is taking advantage of multi-core architectures, software tools, and clusters.

John Gustafson, from our Intel Labs, an industry HPC veteran, is my co-author, and I am thrilled to have him speak about Balanced Computing. Wes Shimanek, a colleague of mine at Intel introduced me to John and after listening to his explanation of balanced computing, and his views on what works and what doesn’t, we immediately  knew that John’s expertise will be greatly valued by the IDF audience, and invited John to be part of the talk. John graciously accepted to participate, and I hope that folks interested in computing architectures, especially in the HPC world will make the time to come listen to John’s talk.

I will also be giving you a high level view on the challenges that drive our products and briefly introduce you to the various aspects of our strategy. I will be followed by 3 more talks that will cover the key aspects of what we do at Intel in HPC, Software Tools for Scaling Application Performance Forward (TCIS002), Delivering more to HPC than just Performance (TCIS003), and Intel® Cluster Ready (TCIS009).

I am looking forward to IDF next week. See you all at the developer forum

Nash Palaniswamy (Intel)

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Found this video about how intel IT converted what was a high volume manafacturing facility to a high performance computing datacenter that now is on the top 500 list.   Watch Tom Greenbaum, Data Center Operations Manager for Intel IT, provide a description of this retro-fit and tour of the new facility.

 

Some key facts highlighted in the video

  • avoided several million $ in facility cost avoidance
  • landed traditional enterprise environment in raised floor, hot/cold aisle design in one section of facility
  • landed HPC environmet on existing concrete slab floor which enabled higher density deployment of servers
  • 6M Watt, 10K server capacity (4.7k today)
  • room to grow for future to support data center consolidation

 

chris

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At Intel when we think of scaling performance forward we think of one word, evolution, not revolution.

 

By evolution we mean developing high performance computing solutions that offer you the balance your applications require in order to deliver the best performance they can.  We do not maximize processor performance without matching it with the necessary memory capacity, bandwidth and system i/o.  We look to match these important components of performance to insure the data is where it needs to be, when it is needed to be in order to quickly and efficiently change it into actionable information.  We maximize your performance by minimizing your latencies.

 

Maximize your performance today, simplify your software development needs, and scale your performance forward as newer microarchitectures debut.

 

Seamless performance – bigger science – that is what we help you achieve faster than ever before.

 

To learn more about our approach to delivering highly effective HPC processors and software tools come to the Sun HPC Virtual Tradeshow on September 17th 2009 starting at 8am PDT.  In the virtual event attend the Intel presentation on “Accelerating Your Applications And Scaling It Forward” by Wes Shimanek & Dr. Nash Palaniswamy at 10:30am PDT.

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I have been around the supercomputing market for over 25 years and have had an opportunity to see some interesting ideas come and go.  Let me share two that I experienced firsthand. 

·         CDC’s Cyber205 or a Cray 1S.  The CRAY-IS and the CDC Cyber 205 both offered effective vector processing, however, code conversion between them may have required some significant algorithmic changes. Cray of course won the HPC race at that time.  Note, the Cyber 205 was a tremendous performer, when you could keep their extreme.ly long vector pipeline busy. However, one branch or gap in the vector processing pipeline would cause a flush of the vector unit and what performance advantage you appeared to have vs. a Cray 1S was quickly erased.

·         An early day accelerator was Floating Point Systems.  In particular the FPS 164 was an awesome “off load” system where the needs of a few users were satisfied with better throughput than the Cray X-MP and Y-MP of the day. Convex, had a better idea.  It was better at serving the needs of more than an FPS 164 and was simpler to develop, maintain and scale software to next generation systems.

So what are the lessons from history? Perhaps it is that there it is there is a tight connection between application, architectures and algorithms and that it is extremely important to maintain a level of application flexibility and versatility in order to adopt new architectures as they become available in the market.  The old adage still remains true, software will outlive the useful life of hardware.  So it is important to be able to quickly adapt new shifts.

The same questions probably still apply today as they did when Cray, CDC and FPS were around.

When does an accelerator computing strategy work best?

The easiest answer is if your application is extremely data parallel in nature, then it may be well suited for an accelerator strategy. The word extremely is the critical part. 

If your application only performs some level of data parallelism and includes task, thread and cluster level parallelism or contains a small fraction of branching or is host to irregular data sizes, then perhaps an accelerator may not be the best fit.

How much real performance will an accelerator strategy deliver? 

Often times we hear claims of 10X, 20X or even greater than 30X. 

These are great headlines, but as many have noted, you need to understand an accelerators impact on the total execution time of your application.  What may have been 10X to 30X or more on a kernel of the application may only deliver a mere 2X to 3X or even less in terms of total application performance improvement.

Of course the real question is what are we really comparing performance speed ups to?

I have seen well tuned software on accelerators compared to “baseline” code running on one core of an old processor.  However, when you use available software technology and turn compiler flags on and add in a math kernel library call the performance on multi-core solutions can jump by over 10X and in some cases can exceed 30X multiples for total execution time.  This standards based accelerated software will scale forward as newer microarchitectures are made available from Intel.

Why is the difference between the promise and the actual performance so great? 

Always a good questionJ. 

The promise deals with a small part or a kernel of the software that is data parallel and can potentially scale linearly as more compute resources are added.  Again if the application is extremely data parallel, then an accelerator strategy may be the correct approach.

However, when the actual performance result, or total application performance, is significantly different it is often because of several things. 

·         One common reason is that you may be comparing optimized software on multi-core systems to optimized software on an accelerator.  When I compare similarly optimized software on a multi-core system I see that 20 – 30X difference often fades to less than 2X  and in most cases better than hardware accelerators.  This is because optimized software on a multi-core solution accelerates all components of the application.

·         Another situation is the bandwidth imbalance of the attach points of the accelerators, typically the attach speeds do not match the memory bandwidth or the ALU speed on the accelerators and the theoretical peak flops are tough to achieve.  Sometimes, for larger workloads due to limited amount of memory on the accelerator card, performance deteriorates.

·         Another situation may be that your application depends on different forms of parallelism which include task, thread or cluster level parallelism and even in some cases sequential forms of your software

So back to the differences in performance between the Cray 1 and CDC Cyber 205.

While Cyber 205 was great at edges of science the Cray proved to be the workhorse of high performance computing.  It offered better system balance than the Cyber 205.  Here is an example, if you take great care to optimize your software for a particular architecture you will no doubt see tremendous performance gains.  However, like the Cyber 205, if you break that pipeline you need to pay for the overhead to restart the long vector pipeline.  Often times, even with today’s accelerators, that start up cost reduces what appears to be stellar performance gains of the Cyber 205 to being no better than, or sometimes, even slower than the Cray 1.  There were of course examples with the Cyber 205, as there is today with accelerators that demonstrate where select sciences can see tremendous advantages over traditional computing solutions.

What other considerations may weigh in your decision to adopt an accelerator strategy?

Are you constantly refining your software?
Many researchers would probably answer yes.  They are constantly refining their software to improve the results the performance or both.

As I mentioned at the beginning of the blog, the old adage still remains true, software will outlive the useful life of hardware.  So it is important to be able to quickly adapt to new shifts.  One way to simplify these moves is to use standards based tools which can give you the flexibility to create applications that can use the multiple types of parallelism mentioned above via tools, compilers, and libraries.  You may also want to use standards based tools to acquire the versatility you need in order to scale your software across multiple architectures – e.g. large, many and heterogeneous cores. 

The caveat with respect to using non standard tools is that you become locked into a specific architecture.  If that architecture from the same vendor would happen to change, you may be required to make some significant changes (e.g. tuning to grain sizes).

Do you want to maintain, support and update multiple code bases?
I don’t.  I want to invest n the development of parallel algorithms.  The old adage is that software will far out live any hardware implementation still applies and I need the flexibility and versatility to quickly and as painlessly as possible be able to adopt new architectures as they are made available.  I do not want to invest in maintaining, supporting and updating an ever increasing set of code streams as newer architectures are made available.

Our team goal at Intel is to develop software tools and hardware technology that can help you scale-forward your application performance to future platforms without requiring a massive rebuild – just drop-in a new runtime that is optimized for the new platform to experience the improvement (akin to the printer/display driver model, buy a new printer/display, install the respective driver, and your system enjoys improved benefits).  That is the goal.

If you want to learn more about what we are doing to deliver high performing HPC solutions that are both flexible and versatile please visit www.intel.com/go/hpc

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Picture1.jpgAt ISC09, the Top 500* results were announced: 399 out 400, nearly 80%, of the world’s supercomputers are using Intel processors.  The Top500 list is based upon one benchmark, Linpack.  While powering most of the world’s fastest computers is a great endorsement of the role Intel’s technology is playing to help solve the most complex high performance computing problems, no one buys a supercomputing machine just to run Linpack.  Linpack is a kernel that does not necessarily resemble any real application.  It’s just one evaluation vector among many. So, should you demand more?

Yes, look beyond the flops:  look at real application performance or benchmarks that might more closely resemble yours, look at the versatility, and look at ease of deployment of your solution.  

Today, Intel processors deliver more performance and throughput in less space and require less power than ever before.  The Intel® Xeon® 5500 Platform delivers up 3X performance over the previous generation Intel Xeon 5400 to decrease your time to discovery.   The Top500 list has 33 new entries based on the Xeon 5500, which launch only 3 months ago. Intel tools (compilers, libraries, and cluster kits) bring new levels of software versatility by enabling HPC users and ISVs write applications that extract peak performance and scale forward.  The Intel’s Cluster Ready program is easing cluster deployments, increasing reliability and lowering TCO by making it simpler to purchase, deploy and manage an HPC cluster.

So while providing flops is great, don’t forget (and demand) to look at real application performance, ask for software tools and technologies that maximize the value of your HPC system.

Jimmy

*Other names and brands may be claimed as the property of others

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I have been watching the social chatter today about the latest Top500 supercomputing list and seeing companies, manufacturers, application vendors and even countries compete for mind share of this most recent list on twitter.

 

However, as I read about and explored this list, the things that jumped out at me were not the who’s number one, two, three … or who grew what number of spots ... but rather the trends that have occurred over time. These trends have not happened in the last 6 months or the last 6 years but instead over the course of nearly a decade of innovation

 

1)      Today, the #10 posting (a cluster using the 3-month old Xeon X5570 processor (Nehalem-EP)) delivers the same FLOPS performance capability equal to the entire June 2000 TOP 500 computers list. (see below)

 

 

top 500 over time jun 09 Performance_Development.png

source: http://www.top500.org/lists/2009/06/performance_development

 

2)      Also, the emergence of multi-core intel-based servers complemented by affordable open-source software solutions have enabled a transformation of how supercomputing performance is delivered. Intel based servers have gone from nearly “0” to nearly “400” over this decade.

 

 

IntelTOP500history.jpg

source: http://www.intel.com/pressroom/images/IntelTOP500history.jpg

 

I recently had the opportunity to co-present a webinar with Matt Jacob’s of Penguin Computing where we talked about how High Performance Computing is changing the way that businesses innovate, research, design, analyze and create. What used to be only done in large datacenters and universities are now available to mainstream IT and businesses.

 

This is extremely important for areas like health care, financial services, manufacturing and many other industries.  Equally important are the software technologies (intel cluster ready software) that can make clustering available and easy to use so that this performance capability can be tapped without a ton of complexity.

 

So, while the Top500 list may be interesting for bragging rights, what excites me and many of the end users that I talk to are is the power, affordability and accessibility that high performance computing has to mainstream business users and the innovation and creativity that brings to the marketplace.

 

How are you using computing perfomance to do things that once were not possible in your business?  Share your story with us !!!

 

Chris

http://twitter.com/chris_p_intel

 

 

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BMW automobiles are known for speed, agility, quality, style and probably some other attributes I’m forgetting. Their IT infrastructure requires the same attributes for them to remain competitive in their industry.

Proactive server refresh, now using Xeon 5500 are part of that equation.  This recent case study outlines how BMWs migration to Xeon 5500 series lowers total cost of ownership and increases flexibility for their business.

Server refresh with Xeon 5500 delivers 30% higher IT performance with 75% less hardware, compared to dual core Xeon 5100 technology. 

The case study also says that BMW’s next refresh target are their RISC based servers

Can you gain a competitive edge replacing aging servers in your infrastructure

Estimate your savings today (www.intel.com/go/xeonestimator)

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Looks like the Intel® Xeon® processor 5500 series is making lots of noise in HPC.  The QPI and integrated memory controller are really providing the boost necessary to make it an all around performance leader for HPC applications.  With all this performance why did Intel add a third memory channel?

The third memory channel enables the platform to support a boat load of memory.  Matter-of-fact, up to 192GB can be supported in a two socket configuration.  It wasn’t too long ago when only 32GB was supported in a dual socket configuration.  By having the ability to support so much memory you can now meet the needs of almost every HPC application.  The 5500 series is intended for all server markets, but let’s face it, with the design changes Intel made with the new architecture the server segment gaining the most benefit appears to be HPC. 

It seemed like yesterday when the only way to have access to large memory configurations was through expensive, proprietary SMP systems.  The HPC market for large SMP systems is still out there but it is shrinking…fast.  Today, we are clustering low cost solutions to create some of the most powerful systems in the world.  Standard components are leading to lower and lower system costs, delivering a price/performance advantage alternative solutions cannot meet.

Now that a single dual socket node can support up to 192GB’s it is important to understand how to get there.  First, to enable 192GB you need 16GB DIMMs x 12 memory slots.  There will be a premium for a 16GB DIMM.  Knowing the options and determining the best, most cost effective solution is going to be dependent upon your environment.  When a large memory node is required, do you purchase the 16GB DIMM’s or go up to a Multi-socket solution?  If I decide to scale back on the memory (use 4GB or 8GB DIMMs instead of 16GB DIMMs) what is the performance impact to my application?  If I am cost sensitive, will the lower cost outweigh the lack of performance?  Can I use SSD’s (Solid State Disk drives) to compensate for any performance loss due to lower memory capacity?  There are many questions to think about when deciding the right configuration for your application and environment and I certainly can’t answer them here.

Let’s not forget the third memory channel enables a different set of optimal memory configurations.  Think x3 when deciding on how much memory to install into your node; 12GB, 24GB, 48GB, etc.  What happens when you don’t use an optimal configuration?  Well it depends, in most cases the impact is minimal, but let me add a bit of context around minimal:

·         Low bandwidth sensitivity (more dependent upon the processor for performance)

        E.g. Monte Carlo, Black-Scholes (financial modeling), BLAST (bioinformatics), AMBER (molecular dynamics)

        Expect less than a 2% difference between memory configurations*

Ÿ  Medium bandwidth sensitivity (somewhat balanced between memory and CPU usage)

        E.g. CFD, Explicit FEA, Implicit FEA (with robust I/O system)

        Expect approx. 5% degradation for non-optimal symmetrical configurations*

Ÿ  High bandwidth sensitivity (high access to the system memory)

        E.g. WRF (weather), POP (climate), MILC (physics), Reservoir Simulation

        Expect approx. 10% degradation for non-optimal symmetrical configurations*

The results are interesting.  In all three cases above, the degraded performance is always better than the performance you would have with only two memory channels.

When you hear about performance impact of non-optimal memory you can see by the examples above, it is application dependent and will not have a severe impact on your overall system performance.   

The Intel Xeon processor 5500 series offers support for huge memory nodes with the addition of the third memory channel.  Memory configurations in multiples of three are ideal, but if you decide to stay with a power of two configuration the performance should still exceed that of a solution based upon only two memory channels.

*Based upon Intel internal measurements

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Often this term is used around the HPC industry referring to the use of HPC to help companies and R&D accelerate the process of innovation.   One close to home example that comes to mind, because I own one of his products, is James Dyson, inventor of the Dyson* vacuum cleaners.   By all means he is a success story, but the road to success, by his own account, was paved by many failures along the way.  According to Dyson, it took him 15 years, nearly his entire savings and 5127 prototypes to develop his creation.   Could HPC technology have streamlined his success?

jamesdyson.jpg

A May 2008 study on the Industrial use of HPC for innovation, sponsored by DARPA, DOE, and Council on Competitiveness, concluded that “HPC-based virtual prototyping and large-scale data modeling provide breakthrough insights that dramatically accelerate and streamline not only ‘upstream’ R&D and engineering, but also ‘downstream’ business processes such as data mining, logistics and custom manufacturing.”    And while, “the United States is the largest consumer of HPC…. some U.S. firms are not applying HPC as aggressively as they could.”

Going back of Dyson’s example, granted a decade ago the use of HPC was limited to few industries, the HPC industry has grown dramatically and so the availability, access and affordability of the computing resources that can significantly streamline the time of discovery to accelerate innovation.  The availability, affordability and combination of powerful workstations, servers, and software can allow a designer to more quickly and efficiently innovate ideas for form, fit and function.  You might want to read this blog on “Why you need a Digital Workbench” by Thor Sewell.   And while cost might be mentioned as one of the barriers to HPC adoption, can you afford to persevere for 15 years and risk your savings?, like Dyson did.  As of matter of fact, companies are innovating around providing HPC services to the “masses”  by lowering the adoption barriers on a “pay-as-you-go-basis.” So while Dyson learned from each of his 5127 so called “failures” over 15 years and nearly his entire savings, HPC technology allows us to accelerate the time from idea to reality process you can more quickly streamline innovation cycle process:  from creating, to simulating, to analyzing , to visualizing.

Jimmy

*Other names and brands may be claimed as the property of others

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My name is Steve Thorne, and this is my first blog post in The Server Room. I’m the product line manager for the Intel Xeon processor 5000 family, and I’m based out of our Hillsboro, Oregon facility. I’ve been looking forward to this blog post for quite some time, since I’ve been meeting with a wide variety of customers over the past few weeks.

 

It’s been just over a month since we introduced the Intel Xeon processor 5500 series (the processor formerly known as “Nehalem-EP”). We are certainly pleased with the response from the industry at this point. Below you will see some of my observations about what has transpired over the first 30 days of release. At the same time, I invite you to share some of your stories about recent installations of the Xeon 5500. Where is it being used? What kind of environments are you using it in? What kind of improvements have you observed in your deployments?

The industry response has been extremely encouraging to me. Our marketing teams spent more than three years diligently preparing for the successful introduction. Some of my observations from the first month include:

·         The list of vendors that support the Xeon 5500 continues to grow. We started with over 70 system manufacturers on March 30, 2009. And on April 14, 2009, Sun Microsystems introduced a new line of x64 blade servers, rack servers and workstations powered by the Intel Xeon processor 5500 series. Of particular interest is the Sun Blade X6275 server module. You can find more info at: http://www.sun.com/solutions/hpc/compute.jsp.

·         I attended our launch event in Santa Clara on March 30, 2009. While at the event, I was pleasantly surprised by the adulation from the customers who were in attendance. In particular, our friends in the Digital Content Creation (DCC) industry are eager to apply the capabilities of the Xeon 5500 for movie special effects and animated features. Being a father of three school age children, I’ve always been fond of our products’ role in the moviemaking process. It’s fun to take your kids to the theater and show them a concrete example of how these incredibly complex processors are used to generate chuckles and special effects in movies ranging from “Cars” to “Monsters vs. Aliens.”

·         Positive recognition has been accorded to the Xeon 5500 from a wide variety of independent press reviewers and articles. A recent internet search revealed almost 875 news references. Recently, George Ou of DailyTech published an interesting article titled “Server roundup: Intel “Nehalem” Xeon versus AMD “Shanghai” Opteron”. You can read the entire article at: http://www.dailytech.com/article.aspx?newsid=15036

·         On May 4, 2009 two independent financial analysts upgraded Intel Corp. stock. Both analysts attributed part of their positive outlook to the introduction and ramp of Xeon 5500 servers.

·         On April 8, 2009 the new Xeon 5500 was a centerpiece of our IDF event in Beijing. In his enterprise key note, Pat Gelsinger said the “Nehalem” microarchitecture has received worldwide acclaim.

·         Customer deployments are underway at leading data centers around the globe – particularly in High Performance Computing (HPC) applications. The HPC accounts encompass university research labs, commercial research and development and large scale clusters. These HPC customers are pushing the outer limits of scientific discovery and innovation, and the best examples are yet to come!

Personally, I was proud to be a part of the introduction of the Xeon 5500. There is a strong sense of satisfaction when the silicon is deployed in real-world environments. And in case you hadn’t heard, we are busy getting ready for the next addition to the Xeon family, codenamed “Westmere-EP.” We expect this new 32nm processor to be socket and pin-compatible with the Xeon 5500, and it will stretch the processor to support six individual CPU cores per socket. Stay tuned for this release in 2010!



 



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Intel® has just launched their latest server processor, the Intel® Xeon® processor 5500 series. It really is a breakthrough processor for Intel and a clearly phenomenal solution for HPC. I was watching a keynote presentation this week and our Vice President was downright giddy about it. What makes this processor such a phenomenal solution for HPC? The answer is really easy; it expands capabilities and shortens users’ time to results. The real question is how does this processor perform so much better than other solutions out there? This answer is a bit more complicated but really fun to answer. Here we go…

Intel® QuickPath Interconnect (QPI) – This is the technology that has replaced the front side bus used in previous generation Xeon® processors. Our previous generation architecture had a bandwidth of 21 GB/s vs. the QPI bandwidth of 46.1 GB/s. This is a speedup of 2.2X, very impressive. For applications that require lots of I/O this is huge. It’s like going from a country back road to an expressway!

Integrated memory controller – Intel has moved the memory controller from the MCH (memory controller Hub) into the processor.  In addition to integrating the memory controller, Intel is now using native DDR3 with speeds up to 1333MHz and three memory channelsper processor; this is a total of 6 memory channels and 64 GB/s of total memory bandwidth for a 2S HPC node.  This is a 3x jump in memory bandwidth from theprevious generation memory controller which only supported speeds up to 1066MHz and 4 memory channels. By integrating the memory controller you are now in closer contact with the processor for lower latency reads and writes.  Intel added two additional memory channel (one per socket) to increase memory capacity and increase the speed to faster reads and writes. 

Energy efficient design – The new Intel® Xeon® processor 5500 series has the dynamic capability of turning off cores when not required. There are more power states and has the ability to transition between power states faster than ever before. Net, net this means less power consumption. By consuming less power and providing world class performance Intel has created a solution that cries out HPC!

By taking advantage of the power saving, Intel has introduced another feature called Intel® Turbo Boost Technology. Intel® Turbo Boost Technology automatically increases processor frequency to boost application performance if thermal headroom is available. Depending on the environment Turbo Boost can increase the processor frequency by as much as 400 MHz!

Another technology supported in the Intel® Xeon processor 5500 series is Hyper-Threading. Intel® Hyper-Threading Technology enables users to run multiple threads on each processing core to increase total application performance while requiring only a fraction of the power that would be necessary to support additional cores. For highly threaded HPC applications this is showing performance gains over 25%.

The Intel® Xeon® processor 5500 series is considered a general purpose processor. However, a closer look at the features and capabilities show that this is one heck of an HPC solution. You can’t help but think Intel knew HPC was an important market segment for servers and they had this in mind as they created the architecture and developed the features.

Well, is Intel pounding their chest…again! They should be. The introduction of the Intel® Xeon® processor 5500 series is breakthrough architecture for HPC users. The industry hasn’t seen generation to generation performance gains like this since the Pentium® Pro was introduced back in the mid 90’s. Congratulations Intel and go ahead and pound that chest, you deserve it!

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That’s right, now you can buy a supercomputer that fits right under your desk. The PSC’s (Personal supercomputer) of today would have been #1 on the Top500 http://www.top500.org in November of 1996. ASCI Red would have been the first system to overtake the performance these small supercomputers can provide today.

So why do you need one of these high performance bad boys? Well, if you are trying to keep up with technology, beat out your competition, and do it at the lowest cost possible then you just better think about buying one. Whether you are in manufacturing, engineering, financial services or life sciences, the benefits offered are huge. You can now simulate vs constructing expensive prototypes, you can do more work at your desk vs. waiting to schedule the job on the oversubscribed cluster and most importantly, it provides the competitive advantage you most dearly need to keep up with your customer’s demands for lower pricing.

There are a couple of very interesting solutions on the market right now that should be considered. One is the Cray CX1. This little monster can support up to 16 quad core processors! With Nehalem soon to launch, that is one heck of a lot of performance.

http://www.cray.com/products/CX1.aspx

The CX1 is also ICR (Intel Cluster Ready) certified. This certification helps to ensure end users the system will provide a positive out-of-box experience. When you install the system and turn it on, it just works. You are maximizing your investment. The last thing a small business needs is to make the investment and then spend days getting the system up and running.

http://software.intel.com/en-us/cluster-ready/

With today’s economy, many businesses are reducing cost and putting off capital expenditures. You have decided to be like many other businesses and wait just one more year to upgrade your current computing system. Your competition decided not to wait. Instead, they purchased a PSC that was Intel Cluster Ready Certified and are now more productive than ever before. They made the investment and are now turning out new designs faster and at a lower cost than ever before. You scratch your head wondering how they do it. As you try to save your business they are growing and winning new business. Sometimes, being aggressive in a difficult time is the prudent thing to do…

Still wondering if this is right for me? Concerned you don’t have the IT staff to support such as beast? You don’t have the budget? Is there software out there I can use? All are good questions/concerns, but the ICR certified PSC minimizes if not eliminates the need for an IT staff. The PSC is one of the most affordable cluster solutions on the market today. It plugs right into your wall socket…you have tamed the beast! As for software, if you are purchasing an ICR certified system, then there are numerous applications available and most likely, one you are already familiar with.

When you are getting ready to make your next workstation or high-end PC purchase, I strongly recommend you consider one of the new kids on the block, the PSC. If it is Intel Cluster Ready Certified, you can rest assured the solution you do buy will just work.

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45nm and Beyond

Posted by Chris P_Intel Apr 23, 2008

Technology moves at such a rapid pace - it can often be mind-boggling. Even working directly with the product teams at Intel, I sometimes have difficulty keeping pace. The good news is that there is a tremendous opportunity today to be captured thanks to this rapid innovation, as well as a steady stream of advanced technology that IT can use to better support business and gain a competitive advantage. Recently I was interviewed by Tim Phillips from the Register about the current 45nm Quad-Core Intel Xeon products and the next generation Intel platforms based on the Nehalem processor.

 

A few years back, Intel fundamentally changed the way we design and develop our underlying micro-processor technology. We streamlined our innovation and accelerated it's pace. Internally, we call this new model Tick-Tock. I like to call it shrink and innovate.

 

A "Tick" is a manufacturing process shrink that delivers smaller silicon with higher speeds, more transistors and lower power consumption (example: moving from 65nm to 45nm process technology). The 45nm quad-core xeon processors (available since Nov '07) utilize unique materials (a high-k, dielectric) that are delivering industry leading performance / watt as measured by the industry's first and only standard benchmark, SPECPower

A "Tock" represents a more extensive architectural innovation (ex. Intel Core Microarchitecture) introducing new micro-architecture features and functionality fully utilizing the higher transistor count set up by the shrink. For Intel Xeon-based servers, the next "tock" is Nehalem. In addition to the new micro-architecture based on 45nm, a system re-design will incorporate next generation memory, I/O and virtualization technology for high performance, high bandwidth solutions compatible with today's leading software solutions

Listen to my podcast interview to learn more about the benefits of using today's products and the timing of next generation Intel technology featuring Nehalem. Is this information useful to you? If so ... how? Have any questions?

 

I'd be happy to hear from you. Chris

 



 

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I just got back from Supercomputing 2007. I remember a conversation 10 or 12 years ago with someone I really respect. That was just after Intel's Supercomputing Division had folded and HPC was in one of its cyclical downturns. Our conversation was roughly about there being no demand for large supercomputers anymore (outside of govt). We surmised that what seemed to be needed most was a cheap gigaflop. To some extent we were right, but mostly we were wrong. Right in that since then, basic engineering analysis has been a driver in the growth of HPC (thinking clusters) . Very wrong in thinking that demand for compute cycles would not continue to increase and a whole host of other things. Big, big miss on that one. If you believe the current market survey numbers, the high end of HPC is mostly stagnant (dollar wise, but not innovation wise), but the low end, small clusters, is growing by leaps and bounds.

 

One of the things I wanted to get a read on at the conference is 10GbE adoption. While a high performance interconnect can be important, especially if you are paying significant amounts for a SW license, so is convenience & ease of use. Particularly if the user base is increasingly non HPC geeks, but mechanical / electrical / aero type engineers who just need to get some work done. Plus, 20 Gb Infiniband / Myrinet / Quadrics might be overkill for small jobs (4 - 16 cluster nodes). My impression is that we still aren't there on 10GbE. I was hoping to see 10GBaseT but it was rare. A couple of vendors had it & could actually show me a switch, but that was it. CX4 really does give me the hives.

 

 

And there is the question of the day - accelerators. What I wanted to understand is the details of how people are programming these things to get an idea of whether the PCIe interface is going to be a bottleneck or not. Are people 'blocking' real codes at coarse enough granularity to avoid a PCIe bottleneck? I mostly struck out. I did have a good chat with the Clearspeed folks. Their programmability looked much better than I expected, but I wonder if it will be too labor intensive for all but the highest ROI situations.

 

 

Another item for me was small form factor boards & density in general. Supermicro, Tyan, Fujitsu, Intel EPSD all had small form factor / high density stuff - for rack n' stack configurations. SGI and Appro showed off what I considered complete systems based on small form factors. There were several more exotic options, but they tend to be outside my customer base.

 

 

The Sun / Rackable 'datacenter in a shipping container' seemed to get a good amount of attention. I'll be very curious to hear why end users like them (assuming they do). Is it reduced CapEx? Is it shorter time to datacenter implementation / expansion?

 

 

Going back to the conversation of a decade ago. We've gotten to the cheap *flop - I'll claim its clusters, or something close to them. Now the focus seems to be on making them 'user friendly' enough for the small industrial cluster crowd. Intel Cluster Ready is one example. WinCCS (or whatever they are calling it today) is another. But there were also a lot of booths emphasizing out of the box experience (SGI & Appro come to mind) or smaller players emphasizing custom configuration (per the application) & hand holding / down the street throat to choke type service levels.

 

 

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Eco-Technology - what does this term mean and why would Intel use it instead of "Green Computing" or something more common?

 

Moore's Law gives us the ability to deliver more performance and greater energy efficiency with each generation of microprocessors - and reducing the energy consumption of our products is far and away the biggest impact Intel can have on carbon footprint.

 

We recently completed an analysis of a high-performance computing configuration that was originally deployed in 2002 (coming in at number 17 in the Top500 Supercomputer list for that year) and is still in use today. This configuration consists of 512 servers fit out into 25 racks using 128 kW and delivers 3.68 TFlops peak on the LINPACK benchmark. Today, that cluster could be replaced with a single rack of roughly 53 blade servers drawing 21 kW and still giving us that 3.7 TFlops of performance (Energy efficiency in the data center). More on whether that level of density is appropriate for everyone later.....

 

 

Think of the incredible increase in productivity - and new innovations - that have been made possible by this phenomenal growth in compute capacity. The explosion of information that's available at our fingertips and the evolution of many aspects of our global economy to bits instead of physical materials.

 

 

And that's really the point of "Eco-Technology" which is defined as an "eco-sensitive" approach to technology that takes into consideration sustainability in both manufacture and end-use of technology.

 

 

So we're increasing both the energy efficiency of our products and we're eliminating potentially harmful materials such as lead and halogen from our manufacturing, but we're also as an industry continuing to contribute to productivity and transformation. Both are important.

 

As companies explore their IT Sustainability programs and we all work to define what green computing should mean, what are your thoughts on how to balance the imperative to do more work, deliver more business value with the rising costs of energy and our collective desire to slow climate change? The US Environmental Protection Agency is contemplating Energy Star for servers. If you were in charge, what criteria would you use to award the label?

 

 

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