Hi All, When using Barrelfish installed on SCC, I found a weird phenomenon that, the more number of cores which I boot Barrelfish on, the less power (exactly the current, the voltage do not change) whole chip&...
Hi, is it possible to configure SCC in such a way that it behaves as it was shared memory system (linux running on cores). i.e creating some structure on core 0 and pass pointer to core 1 where core 1 ca...
Hi, I am experiencing some problem in using TSR to implement a lock. I have written a test case where I access TSR for "core 0" (from core 0). At beginning I set TSR to “1” so that next rea...
Cross post for Nil. ##http://marcbug.scc-dc.com/bugzilla3/show_bug.cgi?id=512 I'm trying to track what cause a segmentation fault in my SCC program. Since I don't have gdb installed in the cores, I try to ma...
I recently found a bug in the implementation of RCCE_reduce. The function runs correctly with the assumption that the root node performing the computation does not require input buffer after calling the function. Th...
Hi all, I want to use RCCE power function in an MPI application but I am not sure whether this is possible using RCKMPI. I wanted to know if there is any way I can use RCCE power functions like RCCE_iset_power...
Hi all, As you know, there is a "1V5" item in the result of "sccBmc -c stutas". Does this mean the voltage and the current of the main memory? I found in the experiments, when the cores are accessing MPB, ...
Hi, Is there a way to know the write combine buffer when is full or flushing? Or, does hardware support register to know status of WCB? Thanks in Advance
Hi, I have some questions regarding MPB behaviour. In my test program I have allocated MPB memory using MPBalloc from config.c/h (provided with AccessFPGA program). Then I create local buffer to hold data and...
Hi, I was experimenting with the Baremichael baremetal framework. Typical applications has the format.. if (get_my_coreid() == 0){ ..... } else if(get_my_coreid() == 1){ ..... } I ...
I have a question about HPCtoolkit on SCC. We have upgraded the SccKit version on SCC to v.1.4.1.3. But we found out that we could not run the HPCtoolkit on this version of Scckit. Before the update it was wo...
Hello, I am using RCKMPI and I am not clear about a few details. For instance, let's assume two processes running on two different tiles (no other processes). Process A sends large (~600KB) data with tag T1 t...
Hi, I am having problem understanding caching on SCC. Currently I am running my own kernel on SCC . I have marked the shared memory (0x8000000- 0x83FFFFFF) as Uncacheable in the Page Tables by setting the PCD bi...
Hi, I am working on SCC baremetal and I need to measure time of some communication between two cores. What is the way to go about it ? Thanks Vaibhav Jain
In an application I was using RCCE_power_set() function to set voltage for a power domain and RCCE_wait_power() function to wait for voltage change to take place. But the problem with this was it took a very long time...
Is it compulsory to call RCCE_wait_power() after each RCCE_iset_power() call ? I have an application which calls RCCE_iset_power() twice with a delay of about 1 min in between. The second call is just ignored, and I a...
Hi, just a short question: Does the SCC hardware support memory access with caching in the L2 cache and write-through mode? Would that use the Write Combine Buffer to collect writes on the same lines? ...
Hi, I'm new to SCC community. When trying to run some example apps from the RCCE library on SCC cores with Linux, I got the following error : isuru@marc040:/shared/isuru$ rccerun -nue 1 -f rc.hos...
Hi, Recently, I've been working on performance counters on SCC. The document I follow is P54C_Architecture_And_Programming_Vol3, Section 26. I've managed to get some performance counter values listed in Table ...
