The many-core chip revolution is well underway.  While there are still hurdles to be overcome, the viability and eventual mainstream commercialization of this technology is just around the corner.

Commenting on the future of HP’s innovation in a Nov 21, 1011 NY Times article, CEO Meg Whitman sees strength in low-power servers like those used in mobile phones and software to analyze very large sets of data for pattern analysis and prediction.

This shift to small, lower watt many-core processing will require “traditional” programmers to utilize frameworks to manage the additional tasks that are required to make their applications rum efficiently on these platforms.

So how do we give these programmers the tools they need to become “parallel programmers”?

According to Intel's Tim Mattson, one way is to separate them into two groups, each with a set of skills:

• Subject Matter Programmers (SMPs) – These are coders familiar with higher-level languages and domain-specific expertise who can build an application that fits the user requirements and productivity needs of a target industry or function.
• Optimization Programmers (OPs) - These are computer and data scientists who can manipulate code at the assembler level.

Next, an “upside-down wedding cake” framework must be developed to form the basis of a software environment that can be used to turn an application expressed in design patterns into working code.

In order to maintain its integrity, SMPs should not be allowed to modify the underlying framework.  This leaves the OPs with the task of developing and maintaining a single-application independent parallel programming structure.

At its highest level, the framework would include structural patterns such as Pipe-and-Filter, Iterative Refinement, and MapReduce.  The goal here is to define the application SW structure and not the underlying computation.

The middle tier would consist of computational patterns including Structured Mesh and Spectral  Methods.  Here we define what takes place inside the boxes created using the structural patterns above.

The lowest tier – parallel patterns – contain parallel algorithms created with Fork-Join or SPMD.

A working example of this approach is the Selective, Embedded, Just-In-Time Specialization (SEJITS) project underway at UC Berkeley http://parlab.eecs.berkeley.edu/research/339 .

Part Two of this blog post will focus on what a Many-Core Operating System design should look like in order to optimize the performance of the applications created using the framework discussed in Part One.

While Intel continues to lead the world in research and development of Many-Core Chips such as the SCC, the Chinese Academy of Sciences is working on a multi-core version of its earlier Godson chips.   According to sources at EET(1),  Godson-T, like IBM's Blue Gene/Q, "seeks to exploit thread-level parallelism  through provision of many—up to 64—simple CPU cores on a die. But unlike Intel's SCC and Blue Gene/Q, which can count on having the finest  scientific programmers, Godson-T is aimed at applications coded by teams  less experienced with multiprocessing."

A shortcoming of the Godson chipsets are a lack of x86 support.  Like SCC, however, they do support Linux-based applications.

During a recent presentation at the annual Hot Chips conference, Godson researcher, Dongrui Fan described the philosophy behind their many-core offering.  Here are some of the observations by those in attendence: "On the surface, the Godson T architecture is not unlike those of other many-core offerings. There is an array  of relatively simple MIPS-derived cores, each with its own cache, local  memory, and connections to the rest of the die, and all unified by a large  L2.

But instead of a complex, custom-designed central crossbar,  Godson’s cores are arranged as an array with vertical and horizontal  connections between elements. Each core includes an internal router that  permits low-latency routing to neighbors and worm-hole routing across  the die. There are actually two physically independent networks,  permitting low latency even when some cores are doing high-bandwidth DMA  bursts.

There is a chip-wide coherency scheme based not on conventional bus  snooping or directory structures, but on a mutual-exclusion lock  instruction and on an additional hardware block that watches the bus and  detects deadlocks."

There is also, in each core, a Data Transfer  Agent—essentially a super DMA controller—that accelerates movement of  complicated data structures over the on-chip networks. The hope,  according to presenter Dongrui Fan, is that these structures will speed  implementation of thread-rich codes on the chip.

And so, the race to produce the next-gen cloud computer continues...stay tuned!

(1) http://www.eetimes.com/design/eda-design/4219256/Hot-Chips--the-puzzle-of-many-cores