Intel Communities : Discussion List - Many-core Applications Research Community

Weird phenomenon about power of SCC chip: more cores booted, less power comsumption

webadmin@intel.com — Mon, 14 Jan 2013 15:40:58 GMT

Hi All,

When using Barrelfish installed on SCC, I found a weird phenomenon that, the more number of cores which I boot Barrelfish on, the less power (exactly the current, the voltage do not change) whole chip consumes. What's more, the decrease of current for each booted core is nearly the same. This is different with my normal ideas, and makes me confused.

Can anybody explain this phenomenon?

Some explaination of the experiment:

1. The menu.lst used to boot Barrelfish contains no application which utilizes DVFS mechanism

2. I used "sccBmc -c status" on MCPC to monitor the power of the SCC chip, and read the "3V3SCC:" item as voltage and current of the SCC chip.

3. Following table is the decrease of current when different # of cores Barrelfish booted on (voltage keeps at 3.3V):

booted core #	current after booted	decreased current	decreased current per core
0	15.2480	0.0000
4	14.7520	0.4960	0.1240
8	14.2570	0.9910	0.1239
24	12.2770	2.9710	0.1238
32	11.3860	3.8620	0.1207
48	9.5050	5.7430	0.1196

Thanks,

Zhiquan

SCC as a shared memory system

webadmin@intel.com — Thu, 25 Apr 2013 20:10:16 GMT

Hi,

is it possible to configure SCC in such a way that it behaves as it was shared memory system (linux running on cores). i.e creating some structure on core 0 and pass pointer to core 1 where core 1 can read or write to that structure?

Thank you.

Problem in using TSR to implement lock

webadmin@intel.com — Wed, 17 Apr 2013 19:57:11 GMT

Hi,

I am experiencing some problem in using TSR to implement a lock.

I have written a test case where I access TSR for "core 0" (from core 0). At beginning I set TSR to “1” so that next read-access will read "1" and lock is granted. Then I write “0” to release it (as done in RCCE). But the problem is I can acquire a lock but then program stops there unless I write a value to TSR using “flit widget” (using sccGui).

Another question, from RCCE_admin.c

Semantics of test&set register: a read returns zero if another core has previously read it and no reset has occurred since then. Otherwise, the read returns one.

Does reset means that the core that previously read it writes to TSR?

Am I missing something here?

I have attached my code as well.

Thank you

Can't get core dumps from programs crashed

webadmin@intel.com — Mon, 15 Apr 2013 22:14:00 GMT

Cross post for Nil.

##http://marcbug.scc-dc.com/bugzilla3/show_bug.cgi?id=512

I'm trying to track what cause a segmentation fault in my SCC program. Since I

don't have gdb installed in the cores, I try to make cores to write a core dump

file I can then inspect with gdb.

However I set "ulimit -c unlimited" and I read with "ulimit -a" the line "-c:

core file size (blocks) unlimited" showing core dumps should be

generated. But I can't find any dump after my program segfaults.

How can I get core dumps actived on linux running on scc cores?

Memory consistency issue using RCCE

webadmin@intel.com — Mon, 15 Apr 2013 22:45:30 GMT

Posting this to main forum, incase missed in sub-community.

http://communities.intel.com/message/182388

RCCE bug: Bug in implementation of RCCE_reduce

webadmin@intel.com — Mon, 15 Apr 2013 22:19:02 GMT

I recently found a bug in the implementation of RCCE_reduce. The function runs

correctly with the assumption that the root node performing the computation

does not require input buffer after calling the function. This assumption is

not true always and hence can lead to problems in certain situations.

I know there is a better implementation of RCCE_reduce in rcce_comm library but

thought like I should point out this bug so that it can be corrected in future

release.

Crosspost from:

Bug 511 - Bug in implementation of RCCE_reduce

marcbug.scc-dc.com

Using RCCE alongwith RCKMPI

webadmin@intel.com — Fri, 08 Mar 2013 22:36:07 GMT

Hi all,

I want to use RCCE power function in an MPI application but I am not sure whether this is possible using RCKMPI. I wanted to know if there is any way I can use RCCE power functions like RCCE_iset_power() and RCCE_wait_power() alongwith RCKMPI.

Thanks,

Niteshh

DDR3 power in the result of "sccBmc -c stutas"

webadmin@intel.com — Sat, 02 Mar 2013 13:01:39 GMT

Hi all,

As you know, there is a "1V5" item in the result of "sccBmc -c stutas".

Does this mean the voltage and the current of the main memory?

I found in the experiments, when the cores are accessing MPB, the current value increases significantly.

Why does power of main memory increase while accessing MPB?

Thanks,

Zhiquan

Write Combine Buffer status

webadmin@intel.com — Mon, 25 Feb 2013 15:24:11 GMT

Hi,

Is there a way to know the write combine buffer when is full or flushing?

Or, does hardware support register to know status of WCB?

Thanks in Advance

MPB reading gives incorrect result

webadmin@intel.com — Tue, 19 Feb 2013 15:31:48 GMT

Hi,

I have some questions regarding MPB behaviour.

In my test program I have allocated MPB memory using MPBalloc from config.c/h (provided with AccessFPGA program). Then I create local buffer to hold data and fill it up with user provided string or latter and using memcpy_put I write this buffer to MPB and it works as expected.

Assuming I wrote “Hello ” into my private buffer (size 32) then use memcpy_put to copy it into MPB then the content of MPB looks as follow (using sccDump)

0000000000000000 | 68 65 6c 6c 6f 20 68 65 | hello he

0000000000000008 | 6c 6c 6f 20 68 65 6c 6c | llo hell

0000000000000010 | 6f 20 68 65 6c 6c 6f 20 | o hello

0000000000000018 | 68 65 6c 6c 6f 20 68 65 | hello he

0000000000000020 | 00 00 00 00 00 00 00 00 | ........

0000000000000028 | 00 00 00 00 00 00 00 00 | ........

For reading the MPB I would do opposite where I use memcpy_get to copy content of MPB to private buffer but the results is

hello hehello hehello hehello he

whereas expected result is

hello hello hello hello hello he

Any ideas or suggestion about what is going wrong?

I have attached the source code as well.

Thanks,

Nil

Baremetal applications - separate tasks for cores

webadmin@intel.com — Tue, 04 Dec 2012 23:02:23 GMT

Hi,

I was experimenting with the Baremichael baremetal framework. Typical applications has the format..

if (get_my_coreid() == 0){

.....

}

else if(get_my_coreid() == 1){

.....

}

I tried to eliminate this if blocking and have separate c programs for separate tasks, in the hope I can launch them on any core without having to edit and recompile the code every time. So I built the code and obtained two object files to be run on cores 00 and 01 (using sccMerge).

When I load these two objects into the memory and release the resets, only the code on core 00 runs properly. Also the message passing between the two programs does not happen properly.

Sometimes, the SCC hangs without running at all after releasing the resets and I have to re-initialize the SCC. I'm quite baffled as to what is the reason behind this. Does anyone have any similar experiences?