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    <title>Intel Communities: Message List - L1 and L2 cache</title>
    <link>http://communities.intel.com/community/tech/processors?view=discussions</link>
    <description>Most recent forum messages</description>
    <language>en</language>
    <pubDate>Tue, 03 Apr 2012 14:35:19 GMT</pubDate>
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    <dc:date>2012-04-03T14:35:19Z</dc:date>
    <dc:language>en</dc:language>
    <item>
      <title>Re: L1 and L2 cache</title>
      <link>http://communities.intel.com/message/152977?tstart=0#152977</link>
      <description>&lt;!-- [DocumentBodyStart:7b71eaa4-08b4-4a8a-abbb-dbd3833f0113] --&gt;&lt;div class="jive-rendered-content"&gt;&lt;p&gt;All current Intel processors support SHA-1 software implementations.&amp;nbsp; Intel has done extensive work on optimizing SHA-1 software algorithms for our instruction set.&amp;nbsp; There is a very good article at &lt;a class="jive-link-external-small" href="http://software.intel.com/en-us/articles/improving-the-performance-of-the-secure-hash-algorithm-1/" target="_blank"&gt;http://software.intel.com/en-us/articles/improving-the-performance-of-the-secure-hash-algorithm-1/&lt;/a&gt; that you should read.&lt;/p&gt;&lt;/div&gt;&lt;!-- [DocumentBodyEnd:7b71eaa4-08b4-4a8a-abbb-dbd3833f0113] --&gt;</description>
      <pubDate>Tue, 03 Apr 2012 14:35:19 GMT</pubDate>
      <author>webadmin@intel.com</author>
      <guid>http://communities.intel.com/message/152977?tstart=0#152977</guid>
      <dc:date>2012-04-03T14:35:19Z</dc:date>
      <clearspace:dateToText>1 year, 1 month ago</clearspace:dateToText>
      <clearspace:objectType>0</clearspace:objectType>
    </item>
    <item>
      <title>Re: L1 and L2 cache</title>
      <link>http://communities.intel.com/message/152599?tstart=0#152599</link>
      <description>&lt;!-- [DocumentBodyStart:28c24030-3d16-4199-a549-c3f99a140f2e] --&gt;&lt;div class="jive-rendered-content"&gt;&lt;p&gt;Well it is actually not the same. AES is for encryption, whereas SHA-1 is for hashing.&lt;/p&gt;&lt;p&gt;Can you escalate whether the CPU's support SHA-1 for hashing?&lt;/p&gt;&lt;p&gt;Thanks, &lt;/p&gt;&lt;/div&gt;&lt;!-- [DocumentBodyEnd:28c24030-3d16-4199-a549-c3f99a140f2e] --&gt;</description>
      <pubDate>Thu, 29 Mar 2012 16:16:08 GMT</pubDate>
      <author>webadmin@intel.com</author>
      <guid>http://communities.intel.com/message/152599?tstart=0#152599</guid>
      <dc:date>2012-03-29T16:16:08Z</dc:date>
      <clearspace:dateToText>1 year, 1 month ago</clearspace:dateToText>
      <clearspace:replyCount>1</clearspace:replyCount>
      <clearspace:objectType>0</clearspace:objectType>
    </item>
    <item>
      <title>Re: L1 and L2 cache</title>
      <link>http://communities.intel.com/message/152589?tstart=0#152589</link>
      <description>&lt;!-- [DocumentBodyStart:6ea27f76-db6a-40b5-b92e-f64c8b04cf71] --&gt;&lt;div class="jive-rendered-content"&gt;&lt;p&gt;The database does not mention the SHA-1, however it does mention about Intel Advanced Encryption Standard Instructions (Intel AES-NI), please check page 82 at:&lt;/p&gt;&lt;p&gt;&lt;a class="jive-link-external-small" href="http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-1600-2600-vol-1-datasheet.html" target="_blank"&gt;http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-1600-2600-vol-1-datasheet.html&lt;/a&gt;&lt;/p&gt;&lt;p style="min-height: 8pt; height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;If it is not the same thing, let me know so I will escalate this to the engineering department to confirm if it does support SHA-1 or not.&lt;/p&gt;&lt;/div&gt;&lt;!-- [DocumentBodyEnd:6ea27f76-db6a-40b5-b92e-f64c8b04cf71] --&gt;</description>
      <pubDate>Thu, 29 Mar 2012 16:07:13 GMT</pubDate>
      <author>webadmin@intel.com</author>
      <guid>http://communities.intel.com/message/152589?tstart=0#152589</guid>
      <dc:date>2012-03-29T16:07:13Z</dc:date>
      <clearspace:dateToText>1 year, 1 month ago</clearspace:dateToText>
      <clearspace:replyCount>2</clearspace:replyCount>
      <clearspace:objectType>0</clearspace:objectType>
    </item>
    <item>
      <title>Re: L1 and L2 cache</title>
      <link>http://communities.intel.com/message/152596?tstart=0#152596</link>
      <description>&lt;!-- [DocumentBodyStart:cdf35ac5-06e3-4621-a1cd-3ffed0bff61b] --&gt;&lt;div class="jive-rendered-content"&gt;&lt;p&gt;Thanks Adolfo.&lt;/p&gt;&lt;p&gt;What about SHA-1 encryption? Do they support it?&lt;/p&gt;&lt;/div&gt;&lt;!-- [DocumentBodyEnd:cdf35ac5-06e3-4621-a1cd-3ffed0bff61b] --&gt;</description>
      <pubDate>Thu, 29 Mar 2012 15:12:35 GMT</pubDate>
      <author>webadmin@intel.com</author>
      <guid>http://communities.intel.com/message/152596?tstart=0#152596</guid>
      <dc:date>2012-03-29T15:12:35Z</dc:date>
      <clearspace:dateToText>1 year, 1 month ago</clearspace:dateToText>
      <clearspace:replyCount>3</clearspace:replyCount>
      <clearspace:objectType>0</clearspace:objectType>
    </item>
    <item>
      <title>Re: L1 and L2 cache</title>
      <link>http://communities.intel.com/message/152586?tstart=0#152586</link>
      <description>&lt;!-- [DocumentBodyStart:10222b4d-f4e4-44e2-b4ce-2ff403bfd9a8] --&gt;&lt;div class="jive-rendered-content"&gt;&lt;p&gt;Both processors have the following L1 and L2 cache:&lt;/p&gt;&lt;p&gt;L1 = 32 KB&lt;/p&gt;&lt;p&gt;L2 = 256 KB&lt;/p&gt;&lt;p style="min-height: 8pt; height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;The L1 and L2 cache size is standard, so all current available Intel processors have this same configuration.&lt;/p&gt;&lt;p style="min-height: 8pt; height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Please check page 14 at:&lt;/p&gt;&lt;p&gt;&lt;a class="jive-link-external-small" href="http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-1600-2600-vol-1-datasheet.html" target="_blank"&gt;http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-1600-2600-vol-1-datasheet.html&lt;/a&gt;&lt;/p&gt;&lt;/div&gt;&lt;!-- [DocumentBodyEnd:10222b4d-f4e4-44e2-b4ce-2ff403bfd9a8] --&gt;</description>
      <pubDate>Thu, 29 Mar 2012 14:18:18 GMT</pubDate>
      <author>webadmin@intel.com</author>
      <guid>http://communities.intel.com/message/152586?tstart=0#152586</guid>
      <dc:date>2012-03-29T14:18:18Z</dc:date>
      <clearspace:dateToText>1 year, 1 month ago</clearspace:dateToText>
      <clearspace:replyCount>4</clearspace:replyCount>
      <clearspace:objectType>0</clearspace:objectType>
    </item>
    <item>
      <title>L1 and L2 cache</title>
      <link>http://communities.intel.com/message/152568?tstart=0#152568</link>
      <description>&lt;!-- [DocumentBodyStart:49fc449e-afef-4ce4-a741-308fdb72c86b] --&gt;&lt;div class="jive-rendered-content"&gt;&lt;p&gt;Hello,&lt;/p&gt;&lt;p&gt;I'd like to know the L1 and L2 cache of the following CPU's:&lt;/p&gt;&lt;p&gt;a) Xeon &lt;span style="font-family: Calibri; font-size: 12pt;"&gt;E5-2630L&lt;/span&gt;&lt;/p&gt;&lt;p&gt;&lt;span style="font-family: Calibri; font-size: 12pt;"&gt;b) Xeon &lt;/span&gt;L5640&lt;/p&gt;&lt;p style="min-height: 8pt; height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;I'd also like to know whether they support SHA-1 encryption&lt;/p&gt;&lt;p style="min-height: 8pt; height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Thanks a lot,&lt;/p&gt;&lt;/div&gt;&lt;!-- [DocumentBodyEnd:49fc449e-afef-4ce4-a741-308fdb72c86b] --&gt;</description>
      <pubDate>Thu, 29 Mar 2012 09:16:05 GMT</pubDate>
      <author>webadmin@intel.com</author>
      <guid>http://communities.intel.com/message/152568?tstart=0#152568</guid>
      <dc:date>2012-03-29T09:16:05Z</dc:date>
      <clearspace:dateToText>1 year, 1 month ago</clearspace:dateToText>
      <clearspace:replyCount>5</clearspace:replyCount>
      <clearspace:objectType>0</clearspace:objectType>
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