Intel Communities: Message List

Re: Intel 3210 Chipset - Max. TDP - MCH and ICH included?

webadmin@intel.com — Thu, 05 Nov 2009 16:42:29 GMT

For the MCH and ICH chips, yes. For the entire platform, you have to consider the other components power draw, but I'm sure you know that.

Re: Intel 3210 Chipset - Max. TDP - MCH and ICH included?

webadmin@intel.com — Wed, 04 Nov 2009 17:16:50 GMT

Hi Michael,

No, the MCH is 21.3 watts and the ICH is 4.3 watts. Add them to get the overall chipset power consumption. With the new Nehalem architecture, the MCH is integrated on the CPU, but in this case, you have discrete IC's. Thanks for your question.

Re: How does one start a blog on this site?

webadmin@intel.com — Thu, 15 Oct 2009 18:58:05 GMT

Hi Cliff,

Yes, let's discuss setting up a blog for IBM within the Server Solutions Insider. This forum was created for Intel Partners and we would be glad to have your contribution.

Regards,

Hank

Re: How does one start a blog on this site?

webadmin@intel.com — Wed, 14 Oct 2009 21:39:59 GMT

The Server Room blog is for Intel bloggers only at this time. Thanks for your question.

The Server Room admin.

Re: NIC Teaming Windows 2008 Core

webadmin@intel.com — Tue, 29 Sep 2009 22:32:19 GMT

irst make sure to use the options to install PROSet and ANS when doing the command line install. Even though there is no GUI, the functions will be available via WMI and scripts. See the User Guide or http://support.intel.com/support/network/sb/cs-016040.htm for help on software installation.

Beginning with version 13.3 of Intel® Network Connections software, visual basic scripts are copied to the \Program Files\Intel\NCS2\Scripts directory when Intel® PROSet for Windows* Device Manager is installed.

If Advanced Networking Service (ANS) is not installed, only adapter scripts are copied to the directory. If ANS is installed then team and VLAN scripts are copied to the Scripts directory.

Descriptions of all the scripts are included in dmscript.txt, which is also in the Scripts directory. A couple of examples for creating a team are below.

Use this script to enumerate your adapters. You will need the numbers to create the team.

Adapter_Enumerate.vbs target username password] [help]

Example:

C:\Program Files\Intel\NCS2\Scripts>cscript Adapter_Enumerate.vbs
Microsoft (R) Windows Script Host Version 5.6
Copyright (C) Microsoft Corporation 1996-2001. All rights reserved.
Installed adapters:
1) TEAM : Team #0 - Intel(R) Gigabit ET Dual Port Server Adapter #2
2) TEAM : Team #0 - Intel(R) Gigabit ET Dual Port Server Adapter
3) Intel(R) PRO/1000 PT Server Adapter
4) Intel(R) PRO/1000 MT Network Connection

Use this script for team creation:

Team_CreateTeam.vbs <AdapterList TeamMode TeamName> [target username password] [help]

Example:

C:\Program Files\Intel\NCS2\Scripts>cscript Team_CreateTeam.vbs 1,2,3 SLA TeamJoeThePlumber
Microsoft (R) Windows Script Host Version 5.6
Copyright (C) Microsoft Corporation 1996-2001. All rights reserved.

Specified ports:
1) Intel(R) Gigabit ET Dual Port Server Adapter #2
2) Intel(R) Gigabit ET Dual Port Server Adapter
3) Intel(R) PRO/1000 PT Server Adapter

Attempting to create SLA team with the adapters above...

Call to create team was successful.

Re: Ask a "Nehalem" Expert

webadmin@intel.com — Wed, 16 Sep 2009 18:59:57 GMT

Hi db4, Thanks for your question. I found the information you are looking for here in the Intel® Xeon® Processor 5500 Series, Datasheet Volume 1.

Now, I'm sure you don't want to really read the whole thing, so to make it easier to answer this specific question, here is the section that may interest you.

2.3 Mixing Processors

Intel supports dual processor (DP) configurations consisting of processors:

1. from the same power optimization segment

2. that support the same maximum Intel QuickPath Interconnect and DDR3 memory

speeds

3. that share symmetry across physical packages with respect to the number of

logical processor per package, number of cores per package, number of Intel

QuickPath interfaces, and cache topology

4. that have identical Extended Family, Extended Model, Processor Type, Family Code

and Model Number as indicated by the function 1 of the CPUID instruction

Note: Processors must operate with the same Intel QuickPath Interconnect, DDR3 memory,

and core frequency.

While Intel does nothing to prevent processors from operating together, some

combinations may not be supported due to limited validation, which may result in

uncharacterized errata. Coupling this fact with the large number of Intel Xeon

Processor 5500 series attributes, the following population rules and stepping matrix

have been developed to clearly define supported configurations.

1. Processors must be of the same power-optimization segment. This insures

processors include the same maximum Intel QuickPath interconnect and DDR3

operating speeds and cache sizes.

2. Processors must operate at the same core frequency. Note, processors within the

same power-optimization segment supporting different maximum core frequencies

(e.g. a 2.93 GHz / 95 W and 2.66 GHz / 95 W) can be operated within a system.

However, both must operate at the highest frequency rating commonly supported.

Mixing components operating at different internal clock frequencies is not

supported and will not be validated by Intel.

3. Processors must share symmetry across physical packages with respect to the

number of logical processors per package, number of cores per package (but not

necessarily the same subset of cores within the packages), number of Intel

QuickPath interfaces, and cache topology.

4. Mixing dissimilar steppings is only supported with processors that have identical

Extended Family, Extended Model, Processor Type, Family Code and Model Number

as indicated by the function 1 of the CPUID instruction. Mixing processors of

different steppings but the same model (as per CPUID instruction) is supported.

Details regarding the CPUID instruction are provided in the AP-485,

Intel® Processor Identification and the CPUID Instruction application note and the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.

5. After AND’ing the feature flag and extended feature flags from the installed

processors, any processor whose set of feature flags exactly matches the AND’ed

feature flags can be selected by the BIOS as the BSP. If no processor exactly

matches the AND’ed feature flag values, then the processor with the numerically

lower CPUID should be selected as the BSP.

6. Intel requires that the proper microcode update be loaded on each processor

operating within the system. Any processor that does not have the proper

microcode update loaded is considered by Intel to be operating out of specification.

7. Customers are fully responsible for the validation of their system configuration.

Let us know if this answers your question.

Re: Ask An Expert - The Server Room

webadmin@intel.com — Thu, 10 Sep 2009 22:50:56 GMT

Thanks for your question and our apologies for our delayed response. I am in the process of retiring this thread. If you are still looking for comments & suggestions on your questions, please kindly start a new thread HERE . Thanks for your participation in our forum.

Wm. Hank Lea- Server Room Admin

Re: Ask An Expert - The Server Room

webadmin@intel.com — Thu, 10 Sep 2009 21:38:28 GMT

Wm. Hank Lea- Server Room Admin

Re: Ask An Expert - The Server Room

webadmin@intel.com — Thu, 10 Sep 2009 21:41:44 GMT

Wm. Hank Lea- Server Room Admin

Re: Ask An Expert - The Server Room

webadmin@intel.com — Thu, 10 Sep 2009 21:57:38 GMT

Wm. Hank Lea- Server Room Admin