Intel Communities: Message List

Re: How do I/O ports work on an SCC core?

webadmin@intel.com — Mon, 15 Nov 2010 17:36:03 GMT

During the MARC symposium in Braunschweig last week, I had the same idea as you: To answer I/O port accesses from other cores on the SCC, you would have to forward them via some shared memory protocol. It's not pretty, but should work. For now, I guess, I am going to prototype this on the MCPC. That should be enough to evaluate it.

For the use case: We have modular device models and some BIOS code lying around. It is not trivial, but straight-forward to wire them together to create something that runs an out-of-the-box bootloader (e.g. GRUB or gPXE). From that point, at least our OS (L4 Fiasco) should run unmodified[1], which would be great for further experiments. I hope it is also sufficient to boot an umodified Linux. Of course, you would still need special drivers for efficient I/O (i.e. the upcoming ethernet and framebuffer features), but the diff to vanilla Linux shrinks considerably and you wouldn't have to touch the baroque bootstrap code. The bar for porting other OSs is reduced as well.

Btw, The symposium in Braunschweig has helped me a lot to improve my mental picture of how the SCC works. So thanks for doing that @ Intel.

Re: How do I/O ports work on an SCC core?

webadmin@intel.com — Mon, 01 Nov 2010 12:22:30 GMT

Yes, I meant IN/OUT instructions and to put it in perspective, we are currently evaluating whether device emulation on the SCC is feasible. A desirable goal would be to run unmodified operating systems (not just SCC Linux).

Being able to respond to I/O port accesses from the MCPC is definitely helpful and example code would be more than appreciated. But the original goal of my question was to find out whether you can route them not to the MCPC, but to another core on the mesh. Correct me if I am wrong, it sounds like this should be possible with modifications to the "chipset". The obvious advantage would be that the latency of handling I/O port accesses is greatly reduced.

How do I/O ports work on an SCC core?

webadmin@intel.com — Fri, 29 Oct 2010 12:16:26 GMT

Hello,

I am looking for information on how I/O port accesses work on the SCC. I skimmed through the SCC Linux code and it seems it uses in/out instructions to communicate with the MCPC (in include/asm-i386/mach-mcemu/mcemu_debug.h). Is there any documentation on how this exactly works? I am particularly interested in how port accesses are communicated over the mesh and how the core knows where to route them.

Regards, Julian