Blog Posts From The Data Stack Tagged With supercomputer

Stampede: Driving Force for Innovation

webadmin@intel.com — Wed, 27 Mar 2013 19:56:21 GMT

Every once in a while you get to touch on a project of incredible scope and vision. The Texas Advanced Computing Center system called Stampede is a really good example. The system was launched in January and was dedicated today in a ceremony in Austin and contains not only 12800 Intel® Xeon® E5 processors, but also the first Petascale adoption of Intel® Xeon Phi™ Coprocessors (6880 of em which deliver over 7 additional Petaflops of peak computational performance).. This system was sponsored by the National Science Foundation (NSF) and is the most powerful system in the NSF’s Extreme Science Engineering and Discovery Environment (XSEDE). Its one of the top 10 most powerful supercomputers in the world and one of the most programmable and accessible.

This system is taking on some of the most interesting challenges in Science and Engineering in the world. Stampede was intended to take on problems like modeling climate change, predicting earthquakes, studying viruses DNA and molecular behavior, modeling hurricanes and simulating space.

A couple of my favorite of these from early work on Stampede:

An assistant professor at MIT(my alma mater) is conducting computational studies on Stampede to explore new ideas for how to manipulate the surface of substances to do important tasks—like clean the air—that have never done before. Her studies are trying to convert CO2 into usable industrial materials.

A team at University of Texas at Austin is using Stampede to Map Antartica and its Ice Sheets: Stampede’s advanced design helps researchers map the Antarctic terrain by running thousands of simulations of how the earth, water, ice and wind interact. Scientists can calculate what the earth must be to create the surface effects we see.

Scientists are using Stampede to develop new methods to quickly pull together massive amounts of data from MRI scans and to combine this data with biophysical models to better represent the full extent of tumor growth in a patient. Their research requires large amounts of complex computations and Stampede exactly fills the bill.

When you put it all together, there are a lot of new applications based on the research activities of thousands of scientists over decades.

How can it do that? The system has two portions. It has a traditional cluster architecture based our Xeon E5 processors, but also what the NSF calls their “Innovation Capability” with Intel Xeon Phi coprocessors at its heart. The power in Stampede is that while the Innovation portion of the machine drives up performance per watt, performance density and parallelism to new levels, it does so with a programming model that is completely compatible with the traditional portion of the system. So we get to the point where we can take advantage of the ease of programming of Intel Architecture products combined with the scaling capability of Intel Xeon Phi coprocessors. Research Scientists and Engineers have developed algorithms over many years and realized that code on Intel processors, can follow a straight forward process to transition to the higher core counts and performance density portion of the system. They get to preserve their intellectual legacy and start to stretch for new insights more quickly.

I love it when we focus on the real science and applications in our work. HPC matters most when it changes how people will live in the future. It does this when new technology is born, or new insights brought to science, or new cures found to disease or find more energy reserves.

The new Stampede system will only change the world. That’s what we do at Intel. Stampede’s future is bright. Stampede is due to be upgraded with next generation Intel® Xeon Phi™ products when they become available. We are excited to be a part of this vision.

Hats off to Jay and the team for a job brilliantly begun.

Intel Xeon Phi 5110P Now Generally Available - Time to make the right hand turn.

webadmin@intel.com — Wed, 30 Jan 2013 21:47:42 GMT

For 5 years.. Intel® has been playing the role of the in car navigations system or smart phone… we have been saying to the Technical Computing industry “Get in the right-hand lane, get ready to make a right hand turn --- parallelize your code, thread and vector your application, take advantage of the performance we have and be ready to take advantage of breakthroughs in the future.

Its time to take the turn.

Intel Sr. VP Diane Bryant announced our product line at Supercomputing 12

We are very excited today to announce that the Intel Xeon Phi™ Coprocessor 5110P is now generally available. The Intel Cluster Studio XE 2013 development software tools required to use it are ready, the platforms to support it are ready, and the product itself, shipping to a select few for 4 months or so… is now available to help bring insight to the toughest problems in the industry.

It brings along over a teraflop of peak performance on a chip, the architecture behind the #1 system in the Green500. 7 systems deployed and listed in the Top500 in mere weeks prior to SC12. Major achievements in performance, performance per watt and programmability.

(NICS Glenn Brook at SC12)

Now… I keep cars for a long time… I still have my 1985 Honda Accord … I am a little stubborn about sticking to the path I am on.. I like the confidence of knowing how I am going to get where I need to go… I know I probably would be better off with more airbags, a more powerful transmission, heck even a glove box that works…

So I sympathize with those who haven’t made the turn to parallelism…

You want to keep the car you know…

And That’s fine.. as long as you aren’t in a race..

Today’s technical computing is a sleak luxury sports car.. Parallelism enables HPC customers to not only open up the throttle, but use all of its gears…

If you are doing technical computing today, your imperative is to drive insight faster, gain ground on the solutions more accurately, find the finish line as soon as possible.

To compete, you must compute.

If you are Audi making cars, or Dreamworks making movies, or Intel making chips, or a researcher making new science… you probably wont win without taking advantage of all your data and using all the compute your systems allow. That requires exploiting parallelism…

At least get the best out of the Xeon Processor based Workstation or cluster you have… but If you have highly parallel workloads, its worth considering Intel Xeon Phi products as well. Dreamworks is finding that adding Intel Xeon Phi is speeding their movies into production faster. Customers like NICS are saying Intel Xeon Phi is delivering “unparalleled productivity”.

I get annoyed when my cell phone says “Please turn around .. if possible.. you missed a turn”

Leibniz Supercomputing Centre Scores a Powerful World First with Intel® Xeon® Processor E5 Family

webadmin@intel.com — Sat, 19 Jan 2013 01:48:25 GMT

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Germany’s Leibniz Supercomputing Centre (LRZ) provides computing facilities for Munich’s universities and the Bavarian Academy of Science and Humanities. As part of the Gauss Centre for Supercomputing (GCS), it's also a national center for high-performance computing (HPC) and a leading supercomputing center for the Partnership for Advanced Computing in Europe (PRACE), an affiliation of European organizations dedicated to operating European supercomputing infrastructure and to promote HPC usage throughout Europe. LRZ is operating a new general-purpose HPC platform with over 155,000 Intel® Xeon® processor E5 family cores. Called SuperMUC*, the HPC platform is No. 4 in the TOP500 Supercomputer rankings and the largest Intel-based computer in the world.

“We considered all major vendors for our new supercomputing platform, but the direct liquid cooling and powerful performance, as well as general HPC capacity, convinced us that the IBM platform powered by the Intel Xeon processer E5 family was the right choice for LRZ,” explained LRZ's Dr. Herbert Huber.

To learn more, download our new Leibniz Supercomputing Centre business success story. You can find more like these on Intel.com and iTunes. And to keep up to date on the latest business success stories, be sure to follow ReferenceRoom on Twitter.

*Other names and brands may be claimed as the property of others.

Intel® Xeon Phi™ Coprocessor Delivers Supercomputing Power for JSCC and South Ural State University

webadmin@intel.com — Sat, 19 Jan 2013 01:24:11 GMT

The new Intel® Xeon Phi™ coprocessor delivers highly-parallel processing to power your breakthrough innovations. And two new business success stories show how companies are already using it:

JSCC Breaks Records: Russian Joint Supercomputer Center raises the bar for performance and energy efficiency with Intel Xeon Phi coprocessors.
South Ural State University Leads the Way: Russia's South Ural State University implements highly energy-efficient RSC Tornado SUSU* supercomputer powered by Intel Xeon Phi coprocessors.

You can find more real-world business success stories like these on Intel.com and iTunes. And to keep up to date on the latest business success stories, be sure to follow ReferenceRoom on Twitter.

HPC at Daresbury Science, Monsanto, and University of Oklahoma with Intel Xeon Processor E5 Family

webadmin@intel.com — Tue, 04 Dec 2012 01:12:24 GMT

Each new generation of processors creates opportunities, and the Intel® Xeon® processor E5 family is no exception. See how three research organizations are putting it to work in these new business success stories:

Daresbury Science and Innovation Campus: World-Leading HPC: The Science and Technology Facilities Council (STFC) at Sci-Tech Daresbury unveils a world-leading high-performance computing (HPC) facility for the UK scientific community based on Intel Xeon processors E5-2670.
Monsanto: Expanding the Resources for Next-Generation Seed Discovery: Monsanto increases performance for seed research by up to 28 percent with an expanded HPC cluster based on Intel Xeon processor E5 Family.
University of Oklahoma: Driving Cutting-Edge Research: A new University of Oklahoma HPC cluster built on Intel Xeon processor E5 family boosts performance for research while reducing power consumption.

Find more business success stories like these on Intel.com and iTunes. And to keep up to date on the latest business success stories, be sure to follow ReferenceRoom on Twitter.

Under the Armor of Knights Corner: Intel MIC Architecture at Hotchips 2012

webadmin@intel.com — Thu, 30 Aug 2012 13:38:49 GMT

I’m George Chrysos, and I led the architecture development of the first Intel® Xeon Phi™ Coprocessor, codename Knights Corner, based on the Intel Many-Integrated-Core (Intel MIC) architecture. When Intel kicked off the Knights Corner program, which was first publicly announced at ISC in May 2010 the project was an exciting opportunity to optimize processor architecture for a specific class of workloads. The Intel MIC Architecture specifically targets highly parallel technical applications in physics, chemistry, biology and financial services – so Examples include weather prediction and climate modeling, fluid dynamics, quantum chromo-dynamics, protein folding, genetics, and options modeling. This allowed us to focus our design and adopt a master of some, rather than jack-of-all-trades approach. I refer to this set of workloads as highly-parallel high-performance computing, or highly parallel HPC.

My aspiration for the Intel MIC architecture is to provide an efficient and robust computing platform for scientists and engineers who are improving the lives of people everywhere by advancing medical research to find cures for cancer and other diseases, increasing the early warning notice time for weather disasters, making energy exploration more efficient, facilitating the design and development of new technologies, and improving the efficiency of global trade.

So, what does an architecture that optimizes for highly parallel HPC look like? We started with three premises:

Maximizing reuse of existing software ecosystem and practices, (i.e. the ability to reuse existing source code and support Intel’s standard software development environment) would be important to make the architecture more useful and more widely applicable to our customers;
The applications are very highly parallel, meaning there are plenty of tasks and threads of work;
Power efficiency or performance-per-watt on the target workloads is the key metric of goodness.

Re-use of the existing software ecosystem is a key attribute of the Intel MIC architecture. Knights Corner does not require the workloads to be re-written in a new programming language, or require a programmer to cope with a software-managed memory coherency and consistency model. From a programmer’s standpoint, the architecture is simply a multi-core processor. Knights Corner runs a standard full service OS; it is a networked node that you can telnet into or communicate to via MPI or sockets programming. Fortran, C, C++ code can be compiled and run correctly on the coprocessor. The OpenMP threading library is supported, and multiple MPI tasks can run simultaneously. VTune can be used for performance characterization and tuning, and the standard Intel debuggers, compilers and libraries are available. In short, it’s a just a computer. But one might ask: “what does this support cost?” The answer might surprise you. l estimated the cost of supporting standard Intel CPU specifics in the core at less than 2% of the area -- accounting for the full chip, it is even less. The value to programmers for this minimal investment is huge.

To optimize the architecture for performance/watt of highly parallel HPC workloads we made three architectural investments:

We built cores that are smaller than the Intel® Xeon® processor cores. The Knights Corner cores do less speculative work than these cores. Doing large amounts of speculative instruction processing is a great way to speed up a single thread of execution, but sometimes the speculative work is aborted and does not contribute to program progress. When there are no other threads (or processes) around, this is the right tradeoff, but when there are an abundance of threads, then instead of doing speculative work for a single thread, we simply choose another thread that has instructions ready to go. Speculative work that is aborted consumes energy that in a highly parallel workload we would rather spend on progress being made by another thread. The Knights Corner cores support 4 thread contexts and execute instructions in program order. Also, many micro-architectural choices were made to optimize the cores specifically for HPC workloads. Some of the design decisions we made were: 1) building the L1 data cache to do both a 512b load and a 512b store per cycle, 2) adding a large L2 TLB, 3) providing an ample 512KB L2 cache per core, and 4) adding a hardware pre-fetcher. In total the design choices we made improved Spec CPU FP 2006 by more than 80% per core, per cycle.
We introduced the widest SIMD instruction set offered by Intel to date, at 512-bits. In highly parallel programs, there are frequently inner loops that step regularly through memory, and perform the same math operations repeatedly. When these loops are assembled with traditional scalar instructions, the core incurs energy overhead for processing each instruction (fetching, decoding, reading the register file and the data cache, tracking dependencies, etc). SIMD amortizes that cost by doing all of the bookkeeping once and performing many math operations in just one instruction. In Knights Corner, a single vector floating point multiply-add (vfma) instruction will perform 32 single-precision or 16 double-precision operations. The wide SIMD instructions allow us to offer very high FLOP rates for computationally dense workloads under a constrained power budget. Wider SIMD can be challenging for an auto-vectorizing compiler or even an assembly programmer to use efficiently. The wider the SIMD, the more challenging it is to use all of the parallel ALUs. To mitigate this, the Knights Corner SIMD instruction set supports several new instruction set features. These are 1) mask registers, 2) gather/scatter, and 3) extended math unit operations. Mask registers allow for predicated execution per ALU, which supports vectorization across short conditional branches and supports efficient software pipelining. Gather/scatter instructions are vector loads and stores that are used when the memory address access patterns are not stride-1, but more irregular. To avoid serializing the code in such regions, gather and scatter instructions are supported. The extended math unit operations allow for high performance vectorized transcendental operations: square-root, reciprocal, logarithm and power. In total the wide SIMD instruction set is a great match for highly parallel programs.
To support more than 50 cores, we built a scalable high bandwidth interconnect and memory subsystem. The on-die interconnect is a high bandwidth bi-directional ring topology which connects the cores to one another as well as to many GDDR5 memory controllers. We placed the memory controllers symmetrically on the ring topology to avoid hot-spots and provide a smooth BW response. We also introduced a vector streaming store instruction that reduces the need to use memory BW when writing output-only arrays to memory.

On top of all of that, we put Intel’s world-class power management technology into Knights Corner so that when individual cores are idle, or Knights Corner is not processing anything, it reduces its power consumption proportionately. Knights Corner is a coprocessor to Intel® Xeon® processor, and both processors or one or the other can be used to get the best performance for a particular application. When not processing, Knights Corner consumes as little power as possible.

In summary, we optimized Intel® Xeon Phi™ coprocessor (codename Knights Corner) to deliver leading performance/watt for highly parallel technical computing workloads, while maintaining the Intel values of programmability and effective power management technology. I am looking forward to seeing this product family contributing to scientific and technical progress!

For more take a look at my presentation from Hotchips on the Intel MIC Architecture & the Xeon Phi.

June 2012 Exascalar: Efficiency Dominates HPC

webadmin@intel.com — Wed, 11 Jul 2012 14:03:46 GMT

Please note: A version of this blog appeared as an Industry Perspective on Data Center Knowledge.

The June 2012 Top500 and now the Green500 have been published so it’s about time to update the latest Exascalar analysis.

Exascalar is a way to synthesize the information in both the Top500 Performance ranking and the Green500 Efficiency ranking of supercomputers into one graph oriented toward Exascale computing goals.

Recall it is simply the logarithmic distance of a particular computer in both performance and efficiency from the exascalar goal of 10^18flops in a 20 MegaWatt envelope. An Exascalar of -2 is a factor of 100 away from the Exascale goal.

Here is Exascalar anlysis of the Green500 list just published.

There are several comments that can be made about the graph. The first is characteristic “triangular” shape of the collected data points. This is due to the limitations power places on performance and a cut-off line in performance.This is the first time I've see what may be a cut-off in efficiency but will need to confirm that.

You can also see the dominant BlueGene/Q systems, which occupied roughly the top20 slots of the Green500 list and for the first time also led the Top500. These are the “column” of dots on the right side of the graph.

The green line in the graph is the “top Exascalar” system over the last five years. Over the period, Exascalar has increased a factor of 100 (from -4 to -2). Most of this gain has been in efficiency. In the future I expect almost all gains will be in efficiency (hence the structure of Exascalar graph).

The list of the top Exascalar systems show how the ranking stacks up with both the Performance and Efficiency rankings of the Top500 and Green500, respectively. The efficiency rankings of the BlueGene systems is a bit deceptive since all top 20 Green500 systems were BlueGene with the same (very high) efficiency. Overall BlueGene takes six of the top ten spots. The SPARC64 system, formerly the top system, declined to number 3. There are three Xeon based systems in the top ten.

Last fall the Top10 Supercomputers didn’t change at all but on the Green500 list there was quite a bit of action. This time of course the BlueGene/Q systems dominated both the Top500 and Green500.

In my next blog I’ll discuss the evolution of Exascalar since the last publication.

Intel® Xeon® Processor E5 Family Delivers Extreme Performance for Carestream Health, SDG, and University of Florence

webadmin@intel.com — Sat, 09 Jun 2012 00:45:59 GMT

Servers, workstations, and storage solutions based on the Intel® Xeon® processor E5 family combine performance, built-in capabilities, and cost-effectiveness to make data centers more flexible and efficient. Three new business success stories explain what they’re doing to help Carestream Health, SDG, and University of Florence meet their real-world challenges:

Carestream Health: Supporting medical imaging in the cloud. A leader in medical imaging IT boosts the capacity of its cloud-based medical imaging service with the Intel Xeon processor E5 family.
SDG: Demonstrable benefits. SDG, IT resellers, and their end customers gain from business solution centers standardized on Intel Xeon processors E5 and E7 families.
University of Florence and Avio: Parallel performance. A university turbomachinery research center cuts 260 days from the calculation time for complex aeronautical simulations with the Intel Xeon processors E5 family and 5600 series.

As always, you can find many more success stories like these on the Intel.com Business Success Stories for IT Managers page or the Business Success Stories for IT Managers channel on iTunes. And to keep up to date on the latest business success stories, follow ReferenceRoom on Twitter.

Moore's Law Meets Shrek's Law: DreamWorks on Intel Chip Chat

webadmin@intel.com — Tue, 01 May 2012 17:55:24 GMT

I'm a lover of quality animation, so I was excited to have a chance to have Derek Chan, head of technology for global operations for DreamWorks on Chip Chat talking about how the technologists at DreamWorks are using cutting edge technology to provide a world where the only thing holding back animators is the limits of their imaginations.

Our talk discussed the history of computing use within the animation industry and how new generations of server performance such as Intel's recent launch of the Xeon E5 family of processors directly translate to new levels of animation brilliance on the screen. He also discussed the intersect between Moore's Law and Shrek's Law...something everyone should hear about.

Enjoy the episode and remember to follow @IntelITS for more!

For more check out Intel Chip Chat on Intel.com, iTunes, and SoundCloud.

The Best of HPC and Supercomputing in 2011: Efficiency, Performance and Intel MIC

webadmin@intel.com — Wed, 28 Dec 2011 15:05:08 GMT

When you think of 2011 in the tech world, there tends to be a related supercomputing event attached. ISC 2011, Supercomputing 2011, IDF 2011…2011 was all about events, events, events! This year was also full of big HPC events at Intel. We delivered the initial development units of MIC, and took part in the announcement of the 10-petaflop system in Texas. As 2012 approaches, let’s reminisce on some of the HPC & Supercomputing highlights of 2011:

We read:

Intel MIC Scores 1st Home Run with 10 Petaflop “Stampede” Supercomputer by Joe Curley

Supercomputing 2011 Day 2: Knights Corner shown at 1TF Per Socket by John Hengeveld

Supercomputing 2011: Monday - Intel and the Top500 by John Hengeveld

Accelerating Open Science Research: A Collaboration with TACC by John Hengeveld

High Performance Computing Around the World – The Wandering Geek by John Hengeveld

Linking Efficiency and Performance: Another Look at the Latest Top500 and Green500 by Winston Saunders

We Watched:

At the High Performance Computing mega-briefing at IDF 2011, we talked about Exascale High Performance Computing.

Intel’s Director of High Performance Computing, John Hengeveld discussed Intel’s innovations in High Performance Computing and Intel Many Integrated Core Architecture.

We Listened to:

Just in time for Supercomputing 2011, John Hengeveld and Joe Curley talked about how HPC affects our world and New High Performance Computing Capabilities on Intel Chip Chat.

At IDF2011, James Reinders of Intel’s software group talked about Parallel Programming for HPC and Linux.

As we close the chapter on one year of high performance computing, we look forward to what the future brings. What are your predictions for the next year? How will High Performance Computing evolve? Let us know what you think and comment!

Remember to follow @IntelITS for the latest on all things supercomputing & HPC from Intel!

Supercomputing 2011 Day 2: Knights Corner shown at 1TF Per Socket

webadmin@intel.com — Tue, 15 Nov 2011 23:40:14 GMT

Today Intel shared our point of view on the HPC industry with the media. Intel showed the performance of the Intel Xeon E5 product and we talked about how it is impacting the supercomputing industry. Intel also explained our success in new clusters - like the Purdue Carter Cluster.

The big news was around our acomplishment in 1997. Intel worked with Sandia Labs to create the first system that passed a sustained double precision 1TF measurement. And, Today.. for the first time, Intel showed our first silicon from the Knights Corner Product. It runs. Even more yet, it showed 1 teraflop double precision -- 1997 was dozens of cabinet -- 2011 is a single 22nm chip.

This is a banner day for Intel and a banner day for the HPC community. Jeff Nichols a Director at Oak Ridge National Labs came on stage to tell customers how their efforts to port code to the Intel MIC architecture have been going. They have ported "millions of lines of code... literally in days"

and achieved outstanding productivity on Intel MIC.

The MIC architecture products are first and foremost compute nodes. They run an open source linux OS, they are networked and can run applications. The usage and programming model of HPC are preserved here... not set aside.

My favorite analogy to this is the notion that with most accelerators, you have to do the technical equivalent of burning down the library at Alexandria. You must deny your technical heritage to gain performance. Unlike those accelerators the Intel MIC solution embraces the technical legacy and makes performance available far more broadly.

Intel is changing the technical computing world again... and we were there.

Supercomputing 2011: Monday - Intel and the Top500

webadmin@intel.com — Mon, 14 Nov 2011 22:30:37 GMT

Today, the top500 list has been announced at SC11 in Seattle and it is fascinating. Published twice a year, this list acts like a scorecard on the industry's direction and health.

Intel is once again the #1 processor architecture on the list, fueling 384/500 entries, and providing over 56% of the processing flops on the list. The #1 processor on the list may still be the Xeon Processor 5600 series, but we are very excited to see the first 10 listings of the Xeon Processor E5 family. When these listings combine with the already public announcement of petaflop systems (GENCI, LRZ, IFERC), Sandy Bridge is making a huge impact on the Supercomputing Landscape. While the top10 systems on the list remain unchanged for this cycle, don't expect that to happen again in June 2012

The top500 list brings to light some good data on initial Xeon Processor E5 performance. The top Rmax (Linpack) score for the 10 systems is 146 Gigaflops per socket. This is a record for an IA based processor, well exceeding the new Interlagos systems shown on the list.

In other SC11 news, I get stopped everywhere here for people to tell me how excited they are about the Intel(r) MIC architecture products. They love the programming model, and they like how they can rapidly able to use their previously developed software on the MIC software development vehicle. They have also mentioned how eager they are to see the future performance of the Knights Corner product.

Things are just getting starting here.The show floor opens tonight, and the booth looks great. The flight simulator is thrilling, and I cant wait to get this show on the road!

Supercomputing 2011: Intel Chip Chat on The Ground in Seattle

webadmin@intel.com — Mon, 14 Nov 2011 15:08:01 GMT

Starting Sunday morning, SC11 is now in full swing! We’re on the ground talking to the experts in supercomputing from Intel and around the industry. You could say we’re a bit super charged for supercomputing this week! :-)

The Supercomputing conference is one of the largest HPC events in the United States and in the world with industry representatives, researchers from academia, and everyone in between gathered to share, show, and study the future of high performance computing. And Intel Chip Chat is on scene to bring you the experts live! You’ve got questions on HPC, cluster computing, and everything supercomputing - We’ve got the experts with the answers!

Who do we have? How about: Jon Riley from NCMS; Brock Palen from MLDS; and Arch Robison, Debra Goldfarb, James Reinders, John Hengeveld, and Joe Curley from Intel; to name just few...

Tune in, turn on, tech out live Tuesday & Wednesday November 15/16 from 9:00 AM to 11:45 AM

Get your questions in now, or live to @IntelChipChat or e-mail chipchat@intel.com.

Rethinking Supercomputer Performance and Efficiency for Exascale

webadmin@intel.com — Thu, 20 Oct 2011 17:30:24 GMT

The biggest challenge facing high performance technical computing is to deliver an Exaflop per second. What makes the problem challenging is not just the achievement of that scale of computing performance, but to do it within a “reasonable” power budget of 20MW as Kirk Skaugen recently announced .

It’s a performance goal that cannot be achieved without an efficiency breakthrough. But the problem is more than just efficiency. As one of the smart guys I work with at Intel is fond of pointing out to me (whenever I get too crazy about efficiency), his wrist-watch is extremely energy efficient - but also not useful for computing.

The story is about performance and efficiency. Neither is sufficient. Both are necessary.

So I asked myself, which systems are closest to achieving Exascale goals and how can a rank order be established? Is there an easy way to look at how close we are to that goal?

A good place to start is the Top500, which ranks on performance, and the newer Green500, which ranks solely on efficiency.

The problem with those metrics is that they are mutually independent. For instance in the Top 20 Green 500 you have servers that are near the bottom of the performance heap. And in the upper eschelons of the Top500 you have many inefficient systems.

For our purposes the separation of the Top500 and Green500 does not provide insight to the Exascale goal.

So I started messing around with several way to look at the data over a weekend. I thought I would just share here the one way to look at things that seemed fruitful,

In the graph below I’ve just taken the efficiency and performance data from most recent Green500 List and plotted performance against efficiency on a log scale.

Please click the image for larger view

To the graph I have added four things: 1. the publicly stated Exascale performance and efficiency goal, 2. an arrow indicating a scalar quantity gauging how “far” each point is from the Exascale goal logarithmically, 3. iso-power lines at 2MW and 20MW, and 4. The boundary of the “Top20” based on the scalar value.

One thing I like is about this representation is that systems having either low performance or efficiency are naturally excluded. To rank highly, you need good performance and efficiency.

Does this approach tell us anything new? One way to tell this is to look at the Top10 based on this ranking. NOTE: This is not intended as formal re-analysis of the data - this is a blog exploring a concept only. The Table below shows how the systems stack up.

Please click the image for a larger view

It is clear that while the top “exascalar” ranking closely aligns to performance, efficiency does have a risruptive effect on the ranking. Systems with more balanced scores tend to move up the “exascalar” ranking (for instance the GSIC HP Proliant system, which ranks 4^th in efficiency and 5^th in performance, moves up to 3^rd in this scheme), whereas relatively inefficient systems, even with high performance, tend to move down.

Looking back at the data in the graph, it is certainly intriguing that systems with relatively low performance are, in fact, nearly within the top 20 range of for this “exascalar.” So efficiency leadership may count for something if it can ultimately scale in performance.

What I like about this approach is the easy interpretation of the scalar value - the “number of orders of magnitude” remaining to Exascale. It's an efficiency and a performance problem. A value of three means a factor of one thousand away from the goal of delivering 1 Exaflop in 20MW.

It remains to be seen how the Exascale challenge will be won, of course. New announcements of plans to improve systems are coming out regularly. Perhaps this approach, or one like it, which looks at both efficiency and performance in the nose-bleed range of supercomputing, will get us beyond looking at performance or efficiency separately and help us to understand which architectures, systems, and approaches are best closing the gap to the solution. And that ultimately will translate to a win for everyone.

As always, I’m interested in your thoughts and insights.

Is it helpful to understand how close systems are to exascale levels of capability. Does“exascalar” approach provide insigh into that? Does it address the question, “which system is closest to achieving Exascale goals of performance and efficiency?” better than looking at power and efficiency separately? How would you improve things? (for instance one could plot power instead of efficiency, but when I looked at it it seemed to provide less insight). What alternatives schemes might be proposed as way to look at Performance and Energy Efficiency in supercomputing and what insights do they offer?

Comments are welcome.

Exascale High Performance Computing Discussions at IDF 2011

webadmin@intel.com — Thu, 22 Sep 2011 21:00:47 GMT

I was very excited to host a “megabriefing” for about 100 international press and analysts at IDF 2011 to share some great steps forward we're making in HPC.

We were joined by HPC pioneer Prof. David Patterson of Berkeley and Rob Neely from LLNL. Professor Patterson (one of the minds behind one of the famous seven dwarfs of HPC) shared a vision for the use of computation to achieve a breakthrough in the understanding of the genetics of cancer. Dr. Neely shared his vision of far greater public access to computation at the LLNL open campus.

I had the pleasure to provide background for people on how intel is making a difference in HPC with our Xeon Processor E5 family, and our future MIC coprocessors.

We got some great questions from the audience around the programming model and architectures that will help make exascale a reality, and a few questions around how Intel collaborates with our partners. All in all a very rewarding conversation… catch the video below.